Cite
HARVARD Citation
Albano, D. et al. (n.d.). Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. International journal of circuit theory and applications. pp. 1523-1540. [Online].
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Albano, D. et al. (n.d.). Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. International journal of circuit theory and applications. pp. 1523-1540. [Online].