Calibration algorithm for 16-bit voltage-mode R–2R DAC. Issue 10 (October 2015) - Liang, Yuhua; Zhu, Zhangming; Ding, Ruixue
Abstract A novel calibration algorithm is presented for the 16-bit voltage-mode R–2R Digital-to-Analog converter (DAC). The proposed calibration can be realized with only some digital circuits and an additional calibrating DAC (CaliDAC) identical to the main DAC (MDAC) added. With the weighing-coefficient compressing technology (WCT) adopted, the nonlinearity of the CaliDAC can be compressed when the calibration is implemented, therefore leaving almost no effect on the output. Adopting the segment-calibration technology (SCT), the integral nonlinearity (INL) errors of the output can be calibrated segment by segment. With the proposed calibration algorithm, the INL errors in the final output can be calibrated successfully in the range of [−0.5LSB, 0.5LSB] for 16-bit voltage-mode R–2R DAC.