A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy. (August 2015) - Zhou, Jia; Xu, Lili; Li, Fule; Wang, Zhihua
Abstract A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTAs layout design. Implemented in a 0.18-μm CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.