Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory*Supported by the National Basic Research Program of China under Grant No 2011CBA00602, and the National Key Scientific and Technological Project under Grant No 2013ZX01032001-001-003. (August 2015) - Liu, Li-Fang; Pan, Li-Yang; Zhang, Zhi-Gang; Xu, Jun
<x content-type="archive" xml:space="preserve">Abstract</x> Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 (HTH) as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 (next to blocking oxide) serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the flat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate flat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.