A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs. Issue 6 (June 2015)

• Record Type: Journal Article
• Authors: Manikandan, R.R.; Amrutur, Bharadwaj
• Is Part Of: Microelectronics journal. Volume 46:Issue 6(2015)
• Page Start: 422
• Page End: 430
• Publication Date: 2015-06
• Subjects: Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.03.004
• Languages: English
• ISSNs: 0959-8324

Abstract

<abstract abstract-type="author" id="ab0005"> <title id="sect0005">Abstract</title> <sec> <p id="sp0100">The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in <inline-formula><alternatives><inline-graphic xlink:href="ark:/27927/pgj24fgqr1j" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math altimg="si0008.gif" overflow="scroll" id="d13e665" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mn>0.13</mml:mn><mml:mspace width="0.25em" /><mml:mi mathvariant="normal">μ</mml:mi><mml:mi mathvariant="normal">m</mml:mi></mml:math></alternatives></inline-formula> CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 1.3 V supply voltage and achieves a phase noise of −96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 μA (0.55%) over the VCO control voltage range of 0.3–1.0 V. The closed loop measurements show a minimized static phase error of within ±70 ps and a ≃9 dB reduction in reference spur level across the PLL output frequency range 2.4–2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations.</p> </sec> </abstract>