A 2.45-GHz W-level output power CMOS power amplifier with adaptive bias and integrated diode linearizer. Issue 5 (May 2015) - Ren, Zhi-xiong; Zhang, Ke-feng; Liu, Lan-qi; Chen, Xiao-fei; Liu, Dong-sheng; Liu, Zheng-lin; Zou, Xuecheng
Abstract A high-linearity CMOS power amplifier (PA) operating at 2.45 GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance (<alternatives><inline-graphic xlink:href="ark:/27927/pgjj2krqg5" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" />Cgs</alternatives>) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2 dB, a maximum output power of 30.7 dB m with 29% of peak power added efficiency (PAE) and −30 dBc third-order intermodulation (IMD3) product at 26.4 dB m output power, reaching to excellent tradeoffs between efficiency and linearity.