A ±3.07% frequency variation clock generator implemented using HV CMOS process. Issue 4 (April 2015) - Wang, Chua-Chin; Wang, Deng-Shian; Sung, Tzu-Chiao; Hsieh, Yi-Jie; Lee, Tzung-Je
Abstract In this paper, we propose a clock generator with a feedback TPC (temperature and process compensation) bias circuit fabricated by a high-voltage (HV) CMOS process. Particularly, the feedback TPC bias is composed of an OPA, MOS transistors and resistors, where large BJT devices are no longer needed such that it is easy to be integrated on chip with small area overhead. The feedback TPC bias circuit, including a MOS transistor, four resistors, and a differential amplifier, is used to provide temperature and process compensation. The proposed circuit design is implemented using 0.25 μm 60 V BCD process. Measurement of 10 dies in the range of 0 °C to 100 °C is carried out to verify that the worst frequency drifting error is ±3.07%.