A 0.15‐μm CMOS baseband LSI employing sleep mode with clock‐offset compensation for M2M wireless sensor networks. Issue 5 (23rd May 2015)

• Record Type: Journal Article
• Authors: Suzuki, Kenji; Yamagishi, Akihiro; Harada, Mitsuru
• Is Part Of: IEEJ transactions on electrical and electronic engineering. Volume 10:Issue 5(2015)
• Page Start: 576
• Page End: 584
• Publication Date: 2015-05-23
• Subjects: Electrical engineering -- Periodicals; Electronics -- Periodicals; 621.3
• DOI: 10.1002/tee.22121
• Languages: English
• ISSNs: 1931-4973

Abstract

<abstract abstract-type="main" id="tee22121-abs-0001"> <title> <x xml:space="preserve">Abstract</x> </title> <p id="tee22121-para-0004">This paper describes a wireless baseband large‐scale integration (LSI) that contains a sleep management circuit. The sleep manager performs the sleep‐clock offset compensation and enables a wireless terminal (WT) with a typical crystal oscillator (XO) to remain in sleep mode for a long period while maintaining synchronization with the access point. Lab experiments show that the sleep period reaches 512 s and that, with intermittent operation, the WT maintains synchronization with the access point for 10 days. The LSI's average current consumption is as low as 11 <italic>μ</italic>A for a 128‐s sleep period. A wakeup detection circuit is also implemented in the LSI. This circuit performs paging control instead of a microprocessor unit (MPU) and this helps to reduce current consumption in the MPU and the flash read only memory (ROM). The single‐chip baseband LSI is fabricated using 0.15‐<italic>μ</italic>m CMOS technology. It is 4.6 mm × 4.2 mm in area and consumes 4.0 <italic>μ</italic>A for sleep operation. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.</p> </abstract>