A 5‐Gbps USB3.0 transmitter and receiver linear equalizer. (28th February 2014)

• Record Type: Journal Article
• Authors: Terzopoulos, Nikolaos; Laoudias, Costas; Plessas, Fotis; Souliotis, George; Koutsomitsos, Sotiris; Birbas, Michael
• Is Part Of: International journal of circuit theory and applications. Volume 43:Number 7(2015:Jul.)
• Page Start: 900
• Page End: 916
• Publication Date: 2014-02-28
• Subjects: Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.1982
• Languages: English
• ISSNs: 0098-9886

Abstract

<abstract abstract-type="main"> <title>Summary</title> <p>A USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de‐emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25‐GHz equalizer provides a 10 dB overall gain equalization and 5.5‐dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high‐speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high‐speed applications like the PCI express (PCIe). Copyright © 2014 John Wiley &amp; Sons, Ltd.</p> </abstract>