A power‐area‐efficient, 3‐band, 2‐RX MIMO, TD‐LTE receiver with direct‐coupled ADC. (7th February 2014)

• Record Type: Journal Article
• Authors: Huang, Mo; Chen, Dihu; Wang, Zhao; Guo, Jianping; Dagher, Elias H.; Xu, Bin; Xu, Ken; Ye, Hui; Zheng, Weiguo; Liang, Zhen; Liang, Xiaofeng; Masenten, Wesley K.
• Is Part Of: International journal of circuit theory and applications. Volume 43:Number 6(2015:Jun.)
• Page Start: 806
• Page End: 821
• Publication Date: 2014-02-07
• Subjects: Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.1978
• Languages: English
• ISSNs: 0098-9886

Abstract

<abstract abstract-type="main"> <title>Summary</title> <p>In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐<italic>μ</italic>m CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ∆Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ∆Σ ADC. At 20 MHz bandwidth, the CT ∆Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley &amp; Sons, Ltd.</p> </abstract>