Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations. (20th December 2012)

• Record Type: Journal Article
• Authors: Jahr, Ralf; Calborean, Horia; Vintan, Lucian; Ungerer, Theo; Smari, Waleed; Fiore, Sandro; Trinitis, Carsten; Ranjan, Rajiv; Buyya, Rajkumar; Nepal, Surya; Georgakopulos, Dimitrios
• Is Part Of: Concurrency and computation. Volume 27:Number 9(2015:Jun.)
• Page Start: 2196
• Page End: 2214
• Publication Date: 2012-12-20
• Subjects: Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.2975
• Languages: English
• ISSNs: 1532-0626

Abstract

<abstract abstract-type="main" id="cpe2975-abs-0001"> <title>Summary</title> <p id="cpe2975-para-0001">In the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before production, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objective that needs to be optimized; power consumption, area, and so on have become very important. Thus, the best configurations have to be found in respect to multiple objectives. In this article, we use a multi‐objective design space exploration tool called Framework for Automatic Design Space Exploration (FADSE) to automatically find near‐optimal configurations in the vast design space of a processor architecture together with a tool for code optimizations and hence evaluate both automatically. As example, we use the Grid ALU Processor (GAP) and its postlink optimizer called GAPtimize, which can apply feedback‐directed and platform‐specific code optimizations. Our results show that FADSE is able to cope with both design spaces. Less than 25% of the maximal reasonable hardware effort for the scalable elements of the GAP is enough to achieve the processor's performance maximum. With a performance reduction tolerance of 10%, the necessary hardware complexity can be further reduced by about two‐thirds. The found high‐quality configurations are analyzed, exhibiting strong relationships between the parameters of the GAP, the distribution of complexity, and the total performance. These performance numbers can be improved by applying code optimizations concurrently to optimizing the hardware parameters. FADSE can find near‐optimal configurations by effectively combining and selecting parameters for hardware and code optimizations in a short time. The maximum observed speedup is 15%. With the use of code optimizations, the maximum possible reduction of the hardware resources, while sustaining the same performance level, is 50%.Copyright © 2012 John Wiley & Sons, Ltd.</p> </abstract>