New system software for parallel programming models on the Intel SCC many‐core processor. (10th May 2013)

• Record Type: Journal Article
• Authors: Clauss, Carsten; Lankes, Stefan; Reble, Pablo; Bemmerl, Thomas; Smari, Waleed; Fiore, Sandro; Trinitis, Carsten; Ranjan, Rajiv; Buyya, Rajkumar; Nepal, Surya; Georgakopulos, Dimitrios
• Is Part Of: Concurrency and computation. Volume 27:Number 9(2015:Jun.)
• Page Start: 2235
• Page End: 2259
• Publication Date: 2013-05-10
• Subjects: Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3033
• Languages: English
• ISSNs: 1532-0626

Abstract

<abstract abstract-type="main" id="cpe3033-abs-0001"> <title>Summary</title> <p id="cpe3033-para-0001">Since the beginning of the multicore era, parallel processing has become prevalent across the board. On a traditional multicore system, a single operating system manages all cores and schedules threads and processes among them, inherently supported by hardware‐implemented cache coherence protocols. However, a further growth of the number of cores per system implies an increasing chip complexity, especially with respect to the cache coherence protocols. Therefore, a very attractive alternative for future many‐core systems is to waive the hardware‐based cache coherency and to introduce a software‐oriented message‐passing based architecture instead: a so‐called Cluster‐on‐Chip architecture. Intel's Single‐chip Cloud Computer (SCC), a many‐core research processor with 48 non‐coherent memory‐coupled cores, is a very recent example for such a cluster‐on‐chip architecture. The SCC can be configured to run one operating system instance per core by partitioning the shared main memory in a strict manner. However, it is also possible to access the shared main memory in an unsplit and concurrent manner, provided that either the caches are disabled or the cache coherency is then ensured by software. In this article, we detail our experiences gained while developing low‐level software for message‐passing and shared‐memory programming on the SCC. We present an SCC‐customized MPI library (called SCC‐MPICH) as well as a shared virtual memory system (called MetalSVM) for the SCC. In doing so, we evaluate the potential of both programming models and we show how these models can be improved especially with respect to the SCC's many‐core architecture. Copyright © 2013 John Wiley & Sons, Ltd.</p> </abstract>