4 × 25 Gb/s 2.6 mW/Gb/s parallel optical receiver analog front‐end for 100 Gb/s Ethernet. Issue 4 (April 2015) - Chen, Yingmei; Luo, Xianliang; He, Xiaofei; Zhang, Yunan; Wang, Pengxia
ABSTRACT A design of 4 × 25 Gb/s parallel optical receiver analog front‐end, including transimpedance amplifier (TIA) and limiting amplifier (LA), is presented in this article. It features a pseudodifferential TIA structure to cancel common mode noise and stabilize circuit. The TIA and LA use regulated cascode technique and four stages interleaving active feedback structure to acquire 23.2 GHz bandwidth and 74.3 dBΩ transimpedance gain. The parallel TIA and LA chip occupies 525 × 1835 μm2 area. It consumes 76 mW per channel and the power consumption per bit is only 2.6 mW/Gb/s. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:974–978, 2015