Exploration/exploitation of a hybrid‐enhanced MPSO‐GA algorithm on a fused CPU‐GPU architecture. (30th July 2014)

• Record Type: Journal Article
• Authors: Franz, Wayne; Thulasiraman, Parimala; Thulasiram, Ruppa K.; Hussain, Farookh Khadeer; Wyrzykowski, Roman; Tudruj, Marek
• Is Part Of: Concurrency and computation. Volume 27:Number 4(2015:Mar.)
• Page Start: 973
• Page End: 993
• Publication Date: 2014-07-30
• Subjects: Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3344
• Languages: English
• ISSNs: 1532-0626

Abstract

<abstract abstract-type="main" id="cpe3344-abs-0001"> <title>Summary</title> <p id="cpe3344-para-0001">Recent work in metaheuristic algorithms has shown that solution quality may be improved by composing algorithms with orthogonal characteristics. At the same time, fused CPU‐GPU systems have emerged as a unique platform on which to study these algorithms. Using metaheuristic algorithms requires striking a balance between local and global exploration. There are no governing rules, however, to balance these. In this paper, we study two population‐based metaheuristic algorithms: multi‐swarm particle swarm optimization (MPSO) and genetic algorithms (GAs). We investigate parallel MPSO variants with genetic operators to increase quality: crossover, mutation, swapping, and all three. We develop a hybrid parallel algorithm that combines a slower convergent algorithm (GA) with a faster one (MPSO). The hybrid achieves significant initial improvement in solution quality but no significant difference in the final average fitness. Executing the GA on the GPU requires approximately an order of magnitude less time (0.07–0.18 s) than on the CPU. Our platform is the AMD A8‐3530MX accelerated processing unit that packs four ×86 CPU cores and 80 very long instruction word GPU processing elements. We make effective use of the hierarchical memory structure on the accelerated processing unit, four‐way very long instruction word vectorization, and zero‐copy buffers. Copyright © 2014 John Wiley & Sons, Ltd.</p> </abstract>