Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle‐in‐cell code. (6th March 2014)
- Record Type:
- Journal Article
- Title:
- Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle‐in‐cell code. (6th March 2014)
- Main Title:
- Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle‐in‐cell code
- Authors:
- Vapirev, A.
Deca, J.
Lapenta, G.
Markidis, S.
Hur, I.
Cambier, J.‐L. - Abstract:
- <abstract abstract-type="main" id="cpe3248-abs-0001"> <title>Summary</title> <p id="cpe3248-para-0001">We present initial comparison performance results for Intel many integrated core (MIC), Sandy Bridge (SB), and graphical processing unit (GPU). A 1D explicit electrostatic particle‐in‐cell code is used to simulate a two‐stream instability in plasma. We compare the computation times for various number of cores/threads and compiler options. The parallelization is implemented via OpenMP with a maximum thread number of 128. Parallelization and vectorization on the GPU is achieved with modifying the code syntax for compatibility with CUDA. We assess the speedup due to various auto‐vectorization and optimization level compiler options. Our results show that the MIC is several times slower than SB for a single thread, and it becomes faster than SB when the number of cores increases with vectorization switched on. The compute times for the GPU are consistently about six to seven times faster than the ones for MIC. Compared with SB, the GPU is about two times faster for a single thread and about an order of magnitude faster for 128 threads. The net speedup, however, for MIC and GPU are almost the same. An initial attempt to offload parts of the code to the MIC coprocessor shows that there is an optimal number of threads where the speedup reaches a maximum. Copyright © 2014 John Wiley & Sons, Ltd.</p> </abstract>
- Is Part Of:
- Concurrency and computation. Volume 27:Number 3(2015:Mar.)
- Journal:
- Concurrency and computation
- Issue:
- Volume 27:Number 3(2015:Mar.)
- Issue Display:
- Volume 27, Issue 3 (2015)
- Year:
- 2015
- Volume:
- 27
- Issue:
- 3
- Issue Sort Value:
- 2015-0027-0003-0000
- Page Start:
- 581
- Page End:
- 593
- Publication Date:
- 2014-03-06
- Subjects:
- Parallel processing (Electronic computers) -- Periodicals
Parallel computers -- Periodicals
004.35 - Journal URLs:
- http://onlinelibrary.wiley.com/ ↗
- DOI:
- 10.1002/cpe.3248 ↗
- Languages:
- English
- ISSNs:
- 1532-0626
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 3405.622000
British Library DSC - BLDSS-3PM
British Library STI - ELD Digital store - Ingest File:
- 3805.xml