MultiMLton: A multicore-aware runtime for standard ML. Issue 6 (November 2014)

• Record Type: Journal Article
• Authors: SIVARAMAKRISHNAN, K. C.; ZIAREK, LUKASZ; JAGANNATHAN, SURESH
• Is Part Of: Journal of functional programming. Volume 24:Issue 6(2014)
• Page Start: 613
• Page End: 674
• Publication Date: 2014-11
• Subjects: Functional programming (Computer science) -- Periodicals
• DOI: 10.1017/S0956796814000161
• Languages: English
• ISSNs: 0956-7968

Abstract

<abstract abstract-type="normal"> <title>Abstract</title> <p> <sc>MultiMLton</sc> is an extension of the MLton compiler and runtime system that targets scalable, multicore architectures. It provides specific support for ACML, a derivative of Concurrent ML that allows for the construction of composable <italic>asynchronous</italic> events. To effectively manage asynchrony, we require the runtime to efficiently handle potentially large numbers of lightweight, short-lived threads, many of which are created specifically to deal with the implicit concurrency introduced by asynchronous events. Scalability demands also dictate that the runtime minimize global coordination. <sc>MultiMLton</sc> therefore implements a split-heap memory manager that allows mutators and collectors running on different cores to operate mostly independently. More significantly, <sc>MultiMLton</sc> exploits the premise that there is a surfeit of available concurrency in ACML programs to realize a new collector design that completely eliminates the need for read barriers, a source of significant overhead in other managed runtimes. These two symbiotic features - a thread design specifically tailored to support asynchronous communication, and a memory manager that exploits lightweight concurrency to greatly reduce barrier overheads - are <sc>MultiMLton</sc>'s key novelties. In this article, we describe the rationale, design, and implementation of these features, and provide experimental results over a range of parallel benchmarks and different multicore architectures including an 864 core Azul Vega 3, and a 48 core non-coherent Intel SCC (Single-Cloud Computer), that justify our design decisions.</p> </abstract>