A Study of Self‐Dithering for ΔΣ Fractional‐N PLL. Issue 1 (January 2015)

• Record Type: Journal Article
• Authors: Kato, Yuji; Ioka, Eri; Matsuya, Yasuyuki
• Is Part Of: Electronics and communications in Japan. Volume 98:Issue 1(2015:Jan.)
• Page Start: 9
• Page End: 14
• Publication Date: 2015-01
• Subjects: Electronics -- Periodicals; Telecommunication -- Periodicals; 621.6805
• DOI: 10.1002/ecj.11606
• Languages: English
• ISSNs: 1942-9533

Abstract

<abstract abstract-type="main"> <title>SUMMARY</title> <p>The <inline-formula><alternatives><inline-graphic mimetype="image" xlink:href="ark:/27927/pgh2t48jwwv" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math display="inline" altimg="urn:x-wiley:19429533:ecj11606:equation:ecj11606-math-0003" overflow="scroll" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>Δ</mml:mi><mml:mi>Σ</mml:mi></mml:mrow></mml:math></alternatives></inline-formula> fractional‐N phase‐locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the <inline-formula><alternatives><inline-graphic mimetype="image" xlink:href="ark:/27927/pgh2t48jxsq" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math display="inline" altimg="urn:x-wiley:19429533:ecj11606:equation:ecj11606-math-0004" overflow="scroll" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>Δ</mml:mi><mml:mi>Σ</mml:mi></mml:mrow></mml:math></alternatives></inline-formula> modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the <inline-formula><alternatives><inline-graphic mimetype="image" xlink:href="ark:/27927/pgh2t48jxnh" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math display="inline" altimg="urn:x-wiley:19429533:ecj11606:equation:ecj11606-math-0005" overflow="scroll" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>Δ</mml:mi><mml:mi>Σ</mml:mi></mml:mrow></mml:math></alternatives></inline-formula> modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self‐dithering <inline-formula><alternatives><inline-graphic mimetype="image" xlink:href="ark:/27927/pgh2t48jxjv" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math display="inline" altimg="urn:x-wiley:19429533:ecj11606:equation:ecj11606-math-0006" overflow="scroll" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>Δ</mml:mi><mml:mi>Σ</mml:mi></mml:mrow></mml:math></alternatives></inline-formula> fractional‐N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.</p> </abstract>