An efficient sparse matrix format for accelerating regular expression matching on field‐programmable gate arrays. Issue 1 (10th May 2013)

• Record Type: Journal Article
• Authors: Jiang, Lei; Tan, Jianlong; Tang, Qiu
• Is Part Of: Security and communication networks. Volume 8:Issue 1(2015:Jan.)
• Page Start: 13
• Page End: 24
• Publication Date: 2013-05-10
• Subjects: Computer networks -- Security measures -- Periodicals; Computer security -- Periodicals; Cryptography -- Periodicals; 005.805
• DOI: 10.1002/sec.780
• Languages: English
• ISSNs: 1939-0114

Abstract

<abstract abstract-type="main" id="sec780-abs-0001"> <title>ABSTRACT</title> <p id="sec780-para-0001">Regular expression matching is widely used in many programming languages and applications. A regular expression is transformed into a deterministic finite automata (DFA) for processing. However, the DFA requires large memory resources because of the state blowup problem. Many algorithms have been proposed to compress the DFA storage and generally store the compressed DFA in sparse matrix format. For field‐programmable gate array (FPGA)‐based implementations, operations on sparse matrix consume multiple clock cycles, thus reducing the flexibility and performance of applications. To accelerate the regular expression matching, we present a compact sparse matrix format for storing the compressed DFA transition table on the FPGA. Taking advantage of the special properties of sparse matrices generated by DFAs, we can accomplish one access within a single clock cycle. Furthermore, we develop a regular expression matching engine on a Xilinx (Xilinx Inc. Location: 2100 Logic Dr, San Jose, CA 95124‐3400, USA) Virtex‐6 FPGA chip using this sparse matrix format. Compared with previous solutions, this regular expression matching engine has more flexibility while keeping high compression ratio. The results show that this regular expression matching engine saves 94<italic>%</italic> of memory space compared with the original DFA structure while keeping a fast matching speed. By running multiple engines in parallel, our design achieves a throughput up to 29 Gbps. Copyright © 2013 John Wiley & Sons, Ltd.</p> </abstract>