NMOS contact resistivity reduction with implants into silicides. Issue 1 (9th December 2013)

• Record Type: Journal Article
• Authors: Rao, K. V.; Khaja, Fareen Adeni; Ni, Chi‐Nung; Muthukrishnan, Shankar; Darlak, Andrew; Lei, Jianxin; Brand, Adam; Variam, Naushad; Cristiano, Fuccio; Pichler, Peter; Tavernier, Clément; Windl, Wolfgang
• Is Part Of: Physica status solidi. Volume 11:Issue 1(2014:Jan.)
• Page Start: 174
• Page End: 177
• Publication Date: 2013-12-09
• Subjects: Solid state physics -- Congresses; Solid state physics -- Periodicals; Solid state physics; Conference proceedings; Periodicals; 530.41
• DOI: 10.1002/pssc.201300381
• Languages: English
• ISSNs: 1862-6351

Abstract

<abstract abstract-type="main" xml:lang="en"> <title>Abstract</title> <p>NMOS contact resistivity (ρ<sub>c</sub>) for NiPtSi was reduced by up to 50% by implanting either Se or P into the silicide film, followed by thermally recrystallizing the silicide and activating the implanted species. The silicide module integration included use of plasma pre‐clean, a thin NiPt film, a low temperature soak anneal (RTP1), and millisecond laser anneals for post‐implant anneals (RTP2 and RTP3). Additionally, experiments with Se implants into TiSi<sub>2</sub> achieved 60% reduction in ρ<sub>c</sub> with exclusive use of laser anneals (for both RTP1 and RTP2). The test structures included van der Pauw, transmission line model (TLM) and diodes, all of which are testable after silicidation to extract of silicide phase and sheet resistance (R<sub>s</sub>), silicide/SD external resistance (R<sub>ext</sub>), ρ<sub>c</sub>, and junction breakdown (V<sub>bj</sub>). In order to mimic realistic CMOS process flows, contact chain structures testable after metal‐1 were also used to obtain average resistance/contact and extract contact resistivity. The results in this work demonstrated adequate process window, while maintaining junction characteristics without degradation of R<sub>s.</sub> Laser anneal steps were key enabler to achieve these results, and were designed to prevent dopant deactivation while minimizing diffusion of SD regions for USJ compatibility for sub‐20 nm CMOS nodes. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)</p> </abstract>