Challenges in CMOS‐based images. Issue 1 (9th December 2013)

• Record Type: Journal Article
• Authors: Roy, Francois; Tournier, A.; Wehbe‐Alause, H.; Blanchet, F.; Boulenc, P.; Leverd, F.; Favennec, L.; Perrot, C.; Pinzelli, L.; Gatefait, M.; Cherault, N.; Jeanjean, D.; Carrere, J. P.; Augier, C.; Ricq, S.; Herault, D.; Hulot, S.; Cristiano, Fuccio; Pichler, Peter; Tavernier, Clément; Windl, Wolfgang
• Is Part Of: Physica status solidi. Volume 11:Issue 1(2014:Jan.)
• Page Start: 50
• Page End: 56
• Publication Date: 2013-12-09
• Subjects: Solid state physics -- Congresses; Solid state physics -- Periodicals; Solid state physics; Conference proceedings; Periodicals; 530.41
• DOI: 10.1002/pssc.201300378
• Languages: English
• ISSNs: 1862-6351

Abstract

<abstract abstract-type="main" xml:lang="en"> <title>Abstract</title> <p>High resolution CMOS image sensor demand is driven by consumer applications like mobile phone or digital still camera. To maintain the image quality, we have to save the signal to noise ratio (SNR) despite the number of photons reduction gathered by the pixel. In this paper, we present how back‐side illumination technology could help to recover signal and how to optimize the process and device in order to reduce the noise. A quantum efficiency larger than 70% is targeted to justify efforts done on BSI process development. We also have to pay attention to pixel to pixel crosstalk coming from free carrier diffusion. To overcome this parasitic phenomenon, deep trench isolation (DTI) should be considered in order to significantly reduce crosstalk between two neighboring pixels. The second main noise contributor related to BSI process is the dark current signal. Dark current less than 1 aA per pixel at room temperature is mandatory to save the image quality at low light level. Therefore, all the Si‐SiO<sub>2</sub> interfaces at the pixel side walls have to be processed without any process damage to reduce as much as possible the surface defects. On top of that, side wall implantation and side wall dielectric fabrication have been optimized to reduce this noise source. The pixel layout has to be fully optimized also to collect and store charges properly. With respect to the 3D pixel shape, a new fully depleted pinned photodiode with vertical charge storage and no lag has been developed. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)</p> </abstract>