Challenges in spacer process development for leading‐edge high‐k metal gate technology. Issue 1 (25th November 2013) - Koehler, Fabian; Triyoso, Dina H.; Hussain, Itasham; Antonioli, Bianca; Hempel, Klaus; Cristiano, Fuccio; Pichler, Peter; Tavernier, Clément; Windl, Wolfgang
Abstract Transistor performance is a key enabler for state‐of‐the‐art electronic devices. Besides fast switching performance, low power consumption is a critical parameter for mobile products. The implementation of HfO2 as a gate dielectric with a high permittivity reduces leakage current and power consumption drastically. Metal gates and work function materials are required to adjust Fermi levels and are essential for device performance. In addition to these key elements of high‐k metal gate (HKMG) technology, encapsulation liners and spacers are found to have a significant impact. We show that the performance of HKMG transistors has a strong dependency on the film quality and growth conditions of the SiN spacers. A good conformality and excellent step coverage at low deposition temperature is achieved with an atomic layer deposition (ALD) process using dichlorosilane and ionized radicals of ammonia. This ALD process is superior to standard LPCVD and PECVD processes with regards to thickness control, within‐wafer‐uniformity and matching of the thickness values between dense and isolated transistors. ALD SiN is applied as a spacer to define the implant profiles. The impact of the ALD SiN spacers on transistor universal curve, miller capacitance and Vt is demonstrated. Further application is a hard mask for selective epitaxy of SiGe. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)