High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer. Issue 1 (16th April 2014) - Nag, Manoj; Steudel, Soeren; Bhoolokam, Ajay; Chasin, Adrian; Rockele, Maarten; Myny, Kris; Maas, Joris; Fritz, Thomas; Trube, Jutta; Groeseneken, Guido; Heremans, Paul
Abstract In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO2 as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μFE) of 16.0 cm2/(V.s), sub‐threshold slope (SS−1) of 0.23 V/decade and off‐currents (IOFF) < 1.0 pA. The TFTs with mf‐PVD SiO2 ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO2 ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μFE, SS−1, and IOFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/−1 MV/cm for duration of 104 s. The TFTs with mf‐PVD SiO2 ESL showed lower threshold‐voltage (VTH) shifts compared with TFTs with 300 °C PECVD SiO2 ESL and TFTs with 200 °C PECVD SiO2 ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO2 ESL TFTs to the low hydrogen content of the mf‐PVD SiO2 layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.