A novel MOSFET with vertical signal‐transfer capability for 3D‐structured CMOS image sensors. Issue 3 (May 2014)

• Record Type: Journal Article
• Authors: Goto, Masahide; Hagiwara, Kei; Iguchi, Yoshinori; Ohtake, Hiroshi; Saraya, Takuya; Toshiyoshi, Hiroshi; Hiramoto, Toshiro
• Is Part Of: IEEJ transactions on electrical and electronic engineering. Volume 9:Issue 3(2014)
• Page Start: 329
• Page End: 333
• Publication Date: 2014-05
• Subjects: Electrical engineering -- Periodicals; Electronics -- Periodicals; 621.3
• DOI: 10.1002/tee.21974
• Languages: English
• ISSNs: 1931-4973

Abstract

<abstract abstract-type="main" xml:lang="en"> <title> <x xml:space="preserve">Abstract</x> </title> <p>We have developed a novel MOSFET that can transfer signals vertically without through‐silicon vias but by using a fully depleted silicon‐on‐insulator (FDSOI) structure with its source region connected to the back electrodes as well as the front ones. A prototype MOSFET fabricated using the backside anisotropic wet etching technique has confirmed that the electrical characteristics measured from the front and the back electrodes are identical. The subthreshold factor <italic>S</italic> of the prototype was found to be 64.5 mV/decade, suggesting a good switching performance. Since the double‐sided MOSFET has vertical signal‐transfer capability and excellent operating characteristics, it is expected to contribute to developing a More‐than‐Moore type device of three‐dimensional integration such as pixel‐parallel image sensors. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.</p> </abstract>