Junctionless nanowire transistor fabricated with high mobility Ge channel. Issue 1 (14th October 2013)

• Record Type: Journal Article
• Authors: Yu, Ran; Georgiev, Yordan M.; Das, Samaresh; Hobbs, Richard G.; Povey, Ian M.; Petkov, Nikolay; Shayesteh, Maryam; O'Connell, Dan; Holmes, Justin D.; Duffy, Ray
• Is Part Of: Physica status solidi. Volume 8:Issue 1(2014:Jan.)
• Page Start: 65
• Page End: 68
• Publication Date: 2013-10-14
• Subjects: Solid state physics -- Periodicals; 530.4105
• DOI: 10.1002/pssr.201300119
• Languages: English
• ISSNs: 1862-6254

Abstract

<abstract abstract-type="main" xml:lang="en"> <title>Abstract</title> <p>The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an <italic>I</italic>_ON/<italic>I</italic>_OFF current ratio of 1.2 × 10³ at <italic>V</italic>_D = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)</p> </abstract>