Substrate Engineering by Hexagonal Boron Nitride/SiO2 for Hysteresis‐Free Graphene FETs and Large‐Scale Graphene p–n Junctions1. Issue 10 (9th July 2013)

• Record Type: Journal Article
• Authors: Xu, Hua; Wu, Juanxia; Chen, Yabin; Zhang, Haoli; Zhang, Jin
• Is Part Of: Chemistry, an Asian journal. Volume 8:Issue 10(2013:Oct.)
• Page Start: 2446
• Page End: 2452
• Publication Date: 2013-07-09
• Subjects: Chemistry -- Periodicals; 540.5
• DOI: 10.1002/asia.201300505
• Languages: English
• ISSNs: 1861-4728

Abstract

<abstract abstract-type="main" xml:lang="en"> <title>Abstract</title> <p>We have explored an approach for the fabrication of intrinsic and hysteresis‐free graphene field‐effect transistors (FETs) and for the construction of graphene p–n junctions based on substrate engineering by hexagonal boron nitride (h‐BN)/SiO<sub>2</sub>. The effect of various interfaces on the performance of the graphene FETs was systematically studied by constructing four types of graphene devices (graphene/SiO<sub>2</sub> FETs, graphene/h‐BN FETs, h‐BN/graphene/SiO<sub>2</sub> FETs, and h‐BN/graphene/h‐BN FETs). Graphene/SiO<sub>2</sub> FETs and h‐BN/graphene/SiO<sub>2</sub> FETs always exhibit large hysteresis before and after annealing, whereas graphene/h‐BN FETs and h‐BN/graphene/h‐BN FETs show intrinsic properties after annealing. Raman measurements also indicate that graphene on a SiO<sub>2</sub> substrate contains large amounts of p‐doping, whereas that on a h‐BN substrate is intrinsic. Thus, the graphene/h‐BN interface gives intrinsic and hysteresis‐free graphene FETs, whilst the graphene/SiO<sub>2</sub> interface affords p‐doping and a hysteresis effect in the graphene FETs. This result is because h‐BN serves as an insulation layer, which prevents charge trapping between the graphene and the charge traps at the graphene/SiO<sub>2</sub> interface, which cause the hysteresis. In addition, the negligible electrostatic doping of h‐BN into graphene also ensures the intrinsic and hysteresis‐free properties of graphene/BN/SiO<sub>2</sub> FETs. Moreover, benefitting from the p‐doped and intrinsic features of graphene on SiO<sub>2</sub> and h‐BN substrates, respectively, large‐scale graphene p–n junction superlattices with great potential difference are constructed and integrated into photodetector arrays by substrate engineering with h‐BN/SiO<sub>2</sub>. Efficient hot carrier‐assisted photocurrent was generated by laser excitation at the junction under ambient conditions.</p> </abstract>