A segment‐based sparse matrix–vector multiplication on CUDA. (7th December 2012)

• Record Type: Journal Article
• Authors: Feng, Xiaowen; Jin, Hai; Zheng, Ran; Shao, Zhiyuan; Zhu, Lei
• Is Part Of: Concurrency and computation. Volume 26:Number 1(2014:Jan.)
• Page Start: 271
• Page End: 286
• Publication Date: 2012-12-07
• Subjects: Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.2978
• Languages: English
• ISSNs: 1532-0626

Abstract

<abstract abstract-type="main" id="cpe2978-abs-0001"> <title>SUMMARY</title> <p id="cpe2978-para-0001">The challenge for <italic>Sparse Matrix–Vector multiplication</italic> (SpMV) performance is memory bandwidth, which mostly depends on input matrices and underlying computing platforms. To solve this challenge, many researchers have explored a variety of optimization techniques. One of the most promising aspects focuses on designing storage formats to represent sparse matrices. However, lots of prior storage formats cannot fully take advantage of the underlying computing platforms, resulting in unsatisfactory performance and large memory footprint. Therefore, a novel storage format, called <italic>Segmented Hybrid ELL + Compressed Sparse Row (CSR)</italic> (SHEC for short), is proposed to further improve the throughput and lessen memory footprint on <italic>Graphics Processing Unit</italic> (GPU). SHEC format employs an interleaved combination pattern, which combines certain amount of compressed rows to form a new SHEC row. Segmentation is brought in to balance load and reduce memory footprint. According to the empirical data, an automatic SHEC‐based SpMV is developed to fit for all the matrices. Experimental results show that SHEC approach outperforms the best results of NVIDIA SpMV library and exhibits a comparable performance with state‐of‐the‐art storage formats on the standard dataset. Copyright © 2012 John Wiley &amp; Sons, Ltd.</p> </abstract>