Reversible and DNA computing. (2021)

• Record Type: Book
• Further Information: Note: Hafiz Md. Hasan Babu.
• Authors: Babu, Hafiz M. H, 1966-
• Contents: Preface Acknowledgments xlvii Acronyms xlix Introduction liii 1 Reversible Logic Synthesis 7 1.1 Reversible Logic 7 1.2 Reversible Function 8 1.3 Reversible Logic Gate 8 1.4 Garbage Outputs 10 1.5 Constant Inputs 10 1.6 Quantum Cost 11 1.7 Delay 12 1.8 Power 12 1.9 Area 13 1.10 Hardware Complexity 14 1.11 Quantum Gate Calculation Complexity 15 1.12 Fan-Out 16 1.13 Self-Reversible 16 1.14 Reversible Computation 17 1.15 Area 17 1.16 Design Constraints for Reversible Logic Circuits 18 1.17 Quantum Analysis of Different Reversible Logic Gates 19 1.17.1 Reversible NOT Gate (Feynman Gate) 20 1.17.2 Toffoli Gate 20 1.17.3 Fredkin Gate 21 1.17.4 Peres Gate 21 1.18 Summary 21 2 Reversible Adder and Subtractor Circuits 23 2.1 Reversible Multi-Operand n-Digit Decimal Adder 23 2.1.1 Full Adder 25 2.1.2 Carry Skip Adder 30 2.1.3 Carry Look-Ahead Adder 37 2.2 Reversible BCD Adders 40 2.2.1 Design Procedure of the Reversible BCD Adder 42 2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder 48 2.3 Reversible BCD Subtractor 54 2.3.1 Carry Look-Ahead BCD Subtractor 56 2.3.2 Carry Skip BCD Subtractor 56 2.3.3 Design of Conventional Reversible BCD Subtractor 58 2.4 Summary 64 3 Reversible Multiplier Circuit 65 3.1 Multiplication Using Booth's Recoding 65 3.2 Reversible Gates as Half Adders and Full Adders 66 3.3 Some Signed Reversible Multipliers 68 3.4 Design of Reversible Multiplier Circuit 69 3.4.1 Some Quantum Gates 70 3.4.2 Recoding Cell 71 3.4.3 Partial Product Generation Circuit 77 3.4.4 Multi-Operand Addition Circuit 82 3.4.5 Calculation of Area and Power of n n Multiplier Circuit 83 3.5 Summary 104 4 Reversible Division Circuit 105 4.1 The Division Approaches 105 4.1.1 Restoring Division 105 4.1.2 Non-Restoring Division 106 4.2 Components of Division Circuit 106 4.2.1 Reversible MUX 106 4.2.2 Reversible Register 107 4.2.3 Reversible PIPO Left Shift Register 108 4.2.4 Reversible Parallel Adder 111 4.3 The Design of Reversible Division Circuit 111 4.4 Summary 115 5 Reversible Binary Comparator 117 5.1 Design of Reversible n-Bit Comparator 117 5.1.1 BJS Gate 118 5.1.2 Reversible 1-Bit Comparator Circuit 120 5.1.3 Reversible MSB Comparator Circuit 122 5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell 122 5.1.5 Reversible Single-Bit Less Than Comparator Cell 124 5.1.6 Reversible 2-Bit Comparator Circuit 125 5.1.7 Reversible n-Bit Comparator Circuit 125 5.2 Summary 134 6 Reversible Sequential Circuits 135 6.1 An Example of Design Methodology 135 6.2 The Design of Reversible Latches 138 6.2.1 The SR Latch 138 6.2.2 The D Latch 142 6.2.3 T Latch 145 6.2.4 The JK Latch 147 6.3 The Design of Reversible Master-Slave Flip Flops 147 6.4 The Design of Reversible Latch and the Master-Slave Flip-Flop with Asynchronous SET and RESET Capabilities 150 6.5 Summary 153 7 Reversible Counter, Decoder and Encoder Circuits 155 7.1 Synthesis of Reversible Counter 156 7.1.1 Reversible T Flip-Flop 156 7.1.2 Reversible Clocked T Flip-Flop 156 7.1.3 Reversible Master Slave T Flip-Flop 157 7.1.4 Reversible Asynchronous Counter 159 7.1.5 Reversible Synchronous Counter 160 7.2 Reversible Decoder 162 7.2.1 Reversible Encoder 164 7.3 Summary 166 8 Reversible Barrel Shifter and Shift Register 169 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter 169 8.1.1 Reversible 3 3 Modified BJN Gate 171 8.1.2 Reversible 2's Complement Generator 172 8.1.3 Reversible Swap Condition Generator 174 8.1.4 Reversible Right Rotator 176 8.1.5 Reversible Bidirectional Barrel Shifter 178 8.2 Design Procedure of Reversible Shift Register 179 8.2.1 Reversible Flip-Flop 179 8.3 Summary 191 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations 193 9.1 Reversible Logic Gates 193 9.1.1 RG1 Gate 194 9.1.2 RG2 Gate 194 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations 195 9.2.1 The R-I Gate 195 9.2.2 The R-II Gate 196 9.3 Summary 199 10 Reversible Programmable Logic Devices 201 10.1 Reversible FPGA 202 10.1.1 3 3 Reversible NH Gate 202 10.1.2 4 4 Reversible BSP Gate 203 10.1.3 4-to-1 Reversible Multiplexer 203 10.1.4 Reversible D-Latch 205 10.1.5 Reversible Write Enabled Master Slave Flip-Flop 205 10.1.6 Reversible RAM 206 10.1.7 Design of Reversible FPGA 206 10.2 Reversible PLA 209 10.2.1 The Design Procedure 210 10.3 Summary 219 11 Reversible RAM and Programmable ROM 221 11.1 Reversible RAM 221 11.1.1 3 3 Reversible FS Gate 222 11.1.2 Reversible Decoder 223 11.1.3 Reversible D Flip-Flop 226 11.1.4 Reversible Write-Enabled Master-Slave D Flip-Flop 226 11.1.5 Reversible Random Access Memory 227 11.2 Reversible PROM 230 11.2.1 Reversible Decoder 230 11.2.2 Design of Reversible PROM 231 11.3 Summary 238 12 Reversible Arithmetic Logic Unit 239 12.1 Design of ALU 239 12.1.1 Conventional ALU 240 12.1.2 The ALU Based on Reversible Logic 241 12.2 Design of Reversible ALU 243 12.3 Summary 246 13 Reversible Control Unit 247 13.1 An Example of Control Unit 247 13.2 Different Components of a Control Unit 248 13.2.1 Reversible HL Gate 249 13.2.2 Reversible BJ Gate 250 13.2.3 Reversible 2-to- 4 Decoder 251 13.2.4 Reversible 3- to-8 Decoder 251 13.2.5 Reversible n-to-2n Decoder 253 13.2.6 Reversible J-K Flip-Flop 257 13.2.7 Reversible Sequence Counter 258 13.2.8 Reversible Instruction Register 258 13.2.9 Control of Registers and Memory 260 13.2.10 Construction Procedure and Complexities of the Control Unit 261 13.3 Summary 264 14 Reversible Fault Tolerant Adder Circuits 271 14.1 Properties of Fault Tolerance 272 14.1.1 Parity Preserving Reversible Gates 273 14.2 Reversible Parity Preserving Adders 275 14.2.1 Fault Tolerant Full Adder 276 14.2.2 Fault Tolerant Carry Skip Adder 278 14.2.3 Fault Tolerant Carry Look-Ahead Adder 281 14.2.4 Fault Tolerant Ripple Carry Adder 283 14.3 Summary 284 15 Reversible Fault Tolerant Multiplier Circuit 285 15.1 Reversible Fault Tolerant Multipliers 285 15.1.1 Reversible Fault Tolerant n n Multiplier 286 15.1.2 LMH Gate 286 15.1.3 Partial Product Generation 288 15.1.4 Multi-Operand Addition 290 15.2 Summary 293 16 Reversible Fault Tolerant Division Circuit 295 16.1 Preliminaries of Division Circuits 295 16.1.1 Division Algorithms 296 16.2 The Division Method 297 16.2.1 Floating-Point Data and Rounding 299 16.2.2 Correctly Rounded Division 300 16
• Publisher Details: Hoboken, NJ : John Wiley & Sons, Inc
• Publication Date: 2021
• Copyright Date: 2021
• Extent: 1 online resource
• Subjects: 006.3/842; Molecular computers; TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General; Molecular computers; Electronic books
• Languages: English
• ISBNs: 9781119679431; 1119679435; 9781119679363; 1119679362; 9781119679455; 1119679451
• Related ISBNs: 9781119679424; 1119679427
• Notes: Note: Includes bibliographical references and index.; Note: Description based on online resource; title from digital title page (viewed on February 16, 2021).
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