Architecture of computing systems -- ARCS 2020 : 33rd International Conference, Aachen, Germany, May 25-28, 2020, Proceedings /: 33rd International Conference, Aachen, Germany, May 25-28, 2020, Proceedings. (2020)

• Record Type: Book
• Other Titles: ARCS 2020
• Further Information: Note: André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis (eds.).
• Other Names: Brinkmann, André, 1973-; Karl, Wolfgang; Lankes, Stefan; Tomforde, Sven; Pionteck, Thilo; Trinitis, Carsten; ARCS (Conference), 33rd
• Contents: Main Conference -- Approximate Data Dependence Pro ling based on Abstract Interval and Congruent Domains -- Evaluating Dynamic Task Scheduling with Priorities and Adaptive Aging in a Task-based Runtime System -- An Architecture for Solving the Eigenvalue Problem on Embedded FPGAs -- ECC Memory for Fault Tolerant RISC-V Processors -- 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs -- Towards a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware -- Investigating Transactional Memory for High Performance Embedded Systems -- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs -- Engineering an Optimized Instruction Set Architecture for AMIDAR Processors -- Scaling Logic Locking Schemes to Multi-Module Hardware Designs -- Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs -- FORMUS3IC Workshop -- Scalable, Decentralized Battery Management System Based on Self-Organizing Nodes -- Security Improvements by Separating the Cryptographic Protocol from the Network Stack onto a Multi-MCU Architecture -- Equally Distributed Bus-Communication Access Rights for Inter MCU Communication using Multimaster SPI -- Workshop on Computer Architectures in Space (CompSpace) -- On the Evaluation of SEU Effects on AXI Interconnect within AP-SoCs -- Satellite Onboard Data Reduction using a Risc-V core inside an RTG4-based Data Processing Pipeline -- Workshop on Parallel Systems and Algorithms (PASA) -- Accelerating Real-Time Applications with Predictable Work-Stealing.
• Publisher Details: Cham : Springer
• Publication Date: 2020
• Extent: 1 online resource
• Subjects: 004.2/2; Computer architecture -- Congresses; Computer systems -- Congresses; Electronic books; Electronic books
• Languages: English
• ISBNs: 9783030527945; 3030527948
• Related ISBNs: 303052793X; 9783030527938
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