Computer principles and design in Verilog HDL. (2015)

• Record Type: Book
• Further Information: Note: Yamin Li.
• Authors: Li, Yamin
• Contents: List of Figures xv; ; List of Tables xxvii; ; Foreword xxix; ; Preface xxxi; ; 1 Computer Fundamentals and Performance Evaluation 1; ; 1.1 Overview of Computer Systems 1; ; 1.2 Basic Structure of Computers 8; ; 1.3 Improving Computer Performance 13; ; 1.4 Hardware Description Languages 16; ; Exercises 18; ; 2 A Brief Introduction to Logic Circuits and Verilog HDL 19; ; 2.1 Logic Gates 19; ; 2.2 Logic Circuit Design in Verilog HDL 22; ; 2.3 CMOS Logic Gates 25; ; 2.4 Four Levels/Styles of Verilog HDL 28; ; 2.5 Combinational Circuit Design 34; ; 2.6 Sequential Circuit Design 42; ; Exercises 59; ; 3 Computer Arithmetic Algorithms and Implementations 63; ; 3.1 Binary Integers 63; ; 3.2 Binary Addition and Subtraction 65; ; 3.3 Binary Multiplication Algorithms 74<br />; 3.4 Binary Division Algorithms 84; ; 3.5 Binary Square Root Algorithms 95; ; Exercises 110; ; 4 Instruction Set Architecture and ALU Design 111; ; 4.1 Instruction Set Architecture 111; ; 4.2 MIPS Instruction Format and Registers 117; ; 4.3 MIPS Instructions and AsmSim Tool 118; ; 4.4 ALU Design 136; ; Exercises 140; ; 5 Single-Cycle CPU Design in Verilog HDL 143; ; 5.1 The Circuits Required for Executing an Instruction 143; ; 5.2 Register File Design 148; ; 5.3 Single-Cycle CPU Datapath Design 154; ; 5.4 Single-Cycle CPU Control Unit Design 160; ; 5.5 Test Program and Simulation Waveform 164; ; Exercises 166; ; 6 Exceptions and Interrupts Handling and Design in Verilog HDL 170; ; 6.1 Exceptions and Interrupts 170; ; 6.2 Design of CPU with Exception and Interrupt Mechanism 176; ; 6.3 The CPU Exception and Interrupt Tests 187; ; Exercises 191; ; 7 Multiple-Cycle CPU Design in Verilog HDL 192; ; 7.1 Dividing Instruction Execution into Several Clock Cycles 192; ; 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes 198; ; 7.3 Multiple-Cycle CPU Control Unit Design 201; ; 7.4 Memory and Test Program 208; ; Exercises 211; ; 8 Design of Pipelined CPU with Precise Interrupt in Verilog HDL 212; ; 8.1 Pipelining 213; ; 8.2 Pipeline Hazards and Solutions 219; ; 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes 225; ; 8.4 Precise Interrupts/Exceptions in Pipelined CPU 240; ; 8.5 Design of Pipelined CPU with Precise Interrupt/Exception 248; ; Exercises 265; ; 9 Floating-Point Algorithms and FPU Design in Verilog HDL 266; ; 9.1 IEEE 754 Floating-Point Data Formats 266; ; 9.2 Converting between Floating-Point Number and Integer 268<br />; 9.3 Floating-Point Adder (FADD) Design 273; ; 9.4 Floating-Point Multiplier (FMUL) Design 290; ; 9.5 Floating-Point Divider (FDIV) Design 302; ; 9.6 Floating-Point Square Root (FSQRT) Design 312; ; Exercises 321; ; 10 Design of Pipelined CPU with FPU in Verilog HDL 323; ; 10.1 CPU/FPU Pipeline Model 323; ; 10.2 Design of Register File with Two Write Ports 326; ; 10.3 Data Dependency and Pipeline Stalls 328; ; 10.4 Pipelined CPU/FPU Design in Verilog HDL 335; ; 10.5 Memory Modules and Pipelined CPU/FPU Test 345; ; Exercises 351; ; 11 Memory Hierarchy and Virtual Memory Management 353; ; 11.1 Memory 353; ; 11.2 Cache Memory 359; ; 11.3 Virtual Memory Management and TLB Design 367; ; 11.4 Mechanism of TLB-Based MIPS Memory Management 377; ; Exercises 384; ; 12 Design of Pipelined CPU with Caches and TLBs in Verilog HDL 386; ; 12.1 Overall Structure of Caches and TLBs 386; ; 12.2 Design of Circuits Related to Caches 387; ; 12.3 Design of Circuits Related to TLB 392; ; 12.4 Design of CPU with Caches and TLBs 400; ; 12.5 Simulation Waveforms of CPU with Caches and TLBs 416; ; Exercises 424; ; 13 Multithreading CPU and Multicore CPU Design in Verilog HDL 425; ; 13.1 Overview of Multithreading CPUs 425; ; 13.2 Multithreading CPU Design 428; ; 13.3 Overview of Multicore CPUs 434; ; 13.4 Multicore CPU Design 436; ; Exercises 442; ; 14 Input/Output Interface Controller Design in Verilog HDL 443; ; 14.1 Overview of Input/Output Interface Controllers 443; ; 14.2 Error Detection and Correction 445; ; 14.3 Universal Asynchronous Receiver Transmitter 452; ; 14.4 PS/2 Keyboard/Mouse Interface Design 461; ; 14.5 Video Graphics Array (VGA) Interface Design 466; ; 14.6 Input/Output Buses 483; ; Exercises 507; ; 15 High-Performance Computers and Interconnection Networks 509; ; 15.1 Category of High-Performance Computers 509; ; 15.2 Shared-Memory Parallel Multiprocessor Systems 510; ; 15.3 Inside of Interconnection Networks 514; ; 15.4 Topological Properties of Interconnection Networks 516; ; 15.5 Some Popular Topologies of Interconnection Networks 518; ; 15.6 Collective Communications 521; ; 15.7 Low-Node-Degree Short-Diameter Interconnection Networks 524; ; Exercises 535; ; Bibliography 536; ; Index 539
• Publisher Details: Singapore : Wiley
• Publication Date: 2015
• Copyright Date: 2015
• Extent: 1 online resource (686 pages), illustrations
• Subjects: 621.390285/5133; Verilog (Computer hardware description language); Computer engineering -- Data processing; Computer engineering -- Data processing; Verilog (Computer hardware description language); Electronic books
• Languages: English
• ISBNs: 9781118841129; 1118841123
• Related ISBNs: 9781118841099
• Notes: Note: Includes bibliographical references and index.; Note: Print version record.
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.