Applied reconfigurable computing architectures, tools, and applications : 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, proceedings /: architectures, tools, and applications : 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, proceedings. (©2020)
- Record Type:
- Book
- Title:
- Applied reconfigurable computing architectures, tools, and applications : 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, proceedings /: architectures, tools, and applications : 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, proceedings. (©2020)
- Main Title:
- Applied reconfigurable computing architectures, tools, and applications : 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, proceedings
- Further Information:
- Note: Fernando Rincón, Jesús Barba, Hayden K.H. So, Pedro Diniz, Julián Caba (eds.).
- Other Names:
- Rincón, Fernando
Barba, Jesús
So, Hayden K. H
Diniz, Pedro C
Caba, Julián
ARC (Symposium), 16th - Contents:
- Intro -- Preface -- Organization -- Contents -- Design Methods and Tools -- Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks -- 1 Introduction -- 2 Background -- 3 Gaussian Process with an Analytic Mean Function -- 4 Accelerator and Dataset -- 4.1 Accelerator's Architecture -- 4.2 Dataset -- 5 Evaluation -- 6 Conclusion and Future Work -- References -- Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design -- 1 Introduction -- 2 State of the Art -- 3 Methodology -- 4 Experimental Evaluation 4.1 Experimental Setup -- 4.2 Combinatorial Designs -- 4.3 Sequential Design -- 5 Conclusion -- References -- Optimising Operator Sets for Analytical Database Processing on FPGAs -- 1 Introduction -- 2 Related Work -- 3 Database Primitives -- 4 Optimisation Targets -- 4.1 Hardware Operator Granularity -- 4.2 Matching of Composed Operators -- 5 Results -- 5.1 Evaluation Setup -- 5.2 Optimisation Process -- 5.3 Discussion -- 6 Conclusion -- References -- Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems -- 1 Introduction -- 2 Technical Background 2.1 Basic Concepts on Reconfiguration -- 2.2 IMPRESS -- 2.3 ARTICo3 -- 3 Enhancing Productivity with Advanced Reconfiguration Features -- 4 Integrating IMPRESS in ARTICo3 -- 4.1 Modifications in ARTICo3 Design Flow -- 4.2 Run-Time Reconfiguration Management of Relocatable Bitstreams -- 5 Model-Based Design of HardwareIntro -- Preface -- Organization -- Contents -- Design Methods and Tools -- Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks -- 1 Introduction -- 2 Background -- 3 Gaussian Process with an Analytic Mean Function -- 4 Accelerator and Dataset -- 4.1 Accelerator's Architecture -- 4.2 Dataset -- 5 Evaluation -- 6 Conclusion and Future Work -- References -- Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design -- 1 Introduction -- 2 State of the Art -- 3 Methodology -- 4 Experimental Evaluation 4.1 Experimental Setup -- 4.2 Combinatorial Designs -- 4.3 Sequential Design -- 5 Conclusion -- References -- Optimising Operator Sets for Analytical Database Processing on FPGAs -- 1 Introduction -- 2 Related Work -- 3 Database Primitives -- 4 Optimisation Targets -- 4.1 Hardware Operator Granularity -- 4.2 Matching of Composed Operators -- 5 Results -- 5.1 Evaluation Setup -- 5.2 Optimisation Process -- 5.3 Discussion -- 6 Conclusion -- References -- Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems -- 1 Introduction -- 2 Technical Background 2.1 Basic Concepts on Reconfiguration -- 2.2 IMPRESS -- 2.3 ARTICo3 -- 3 Enhancing Productivity with Advanced Reconfiguration Features -- 4 Integrating IMPRESS in ARTICo3 -- 4.1 Modifications in ARTICo3 Design Flow -- 4.2 Run-Time Reconfiguration Management of Relocatable Bitstreams -- 5 Model-Based Design of Hardware Accelerators -- 6 Experimental Results -- 7 Conclusions -- References -- Chisel Usecase: Designing General Matrix Multiply for FPGA -- 1 Introduction -- 2 High Level Methodology -- 2.1 High Level Description -- 2.2 From Application to Architecture -- 3 Methodology Usecase 4 Results -- 4.1 Experimental Setup -- 4.2 Control of Generated Hardware -- 4.3 Architecture Exploration: Dimensioning the Application -- 4.4 Existing Solutions -- 4.5 Analysis and Contribution -- 5 Conclusion -- References -- Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks -- 1 Introduction -- 2 Related Work -- 3 Cycle-Accurate Debugging by RNN -- 3.1 Design Methodology -- 3.2 RNN Implementation -- 4 Obstacle Avoidance as Use Case -- 5 Results -- 5.1 Resource Utilization -- 5.2 Debugging Through RNNs -- 5.3 Training Dataset Requirement -- 6 Conclusions -- References Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs -- 1 Introduction -- 2 Background and Related Works -- 2.1 Internal Configuration Access Port and Internal Configuration Controller -- 2.2 Dynamically Reconfigurable Processing Module -- 2.3 SRAM-Based FPGAs Radiation Sensitivity and Evaluation Methodologies -- 3 Evaluation Framework -- 3.1 DRPM Setup -- 3.2 Fault Injection Platform -- 4 Experimental Results -- 4.1 SEUs Injection Campaign Results -- Avionic Environment -- 4.2 MBUs Injection Campaign Results -- Space Environment … (more)
- Publisher Details:
- Cham : Springer
- Publication Date:
- 2020
- Copyright Date:
- 2020
- Extent:
- 1 online resource (407 p.)
- Subjects:
- 004
Adaptive computing systems -- Congresses
Computer architecture -- Congresses
Adaptive computing systems
Computer architecture
Electronic books
Conference papers and proceedings - Languages:
- English
- ISBNs:
- 9783030445348
3030445348 - Notes:
- Note: Includes bibliographical references and author index.
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- Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
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- Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.
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- Physical Locations:
- British Library HMNTS - ELD.DS.508445
- Ingest File:
- 03_085.xml