Fan-out wafer-level packaging. (2018)

• Record Type: Book
• Further Information: Note: John H. Lau.
• Authors: Lau, John H
• Contents: Intro; Preface; Acknowledgements; Contents; About the Author; 1 Patent Issues of Fan-Out Wafer-Level Packaging; 1.1 Introduction; 1.2 Functions of Semiconductor Packaging; 1.3 Level of Semiconductor Packaging; 1.4 Patents Impacting the Semiconductor Packaging; 1.4.1 Leadframe; 1.4.2 Organic Substrate with Solder Balls; 1.4.3 Fan-In Wafer-Level Packaging; 1.4.4 Fan-Out Wafer-Level Packaging; 1.5 Major Claims of Infineon's Patent; 1.6 TSMC InFO-WLP; 1.7 Fraunhofer IZM FOPLP; 1.8 Ball/Bump Pitch/Size of PBGA, fcPBGA, WLCSP, and FOWLP; 1.9 Summary and Recommendations; References. 2 Flip Chip Technology Versus FOWLP2.1 Introduction; 2.2 Wafer Bumping; 2.2.1 C4 Bumps; 2.2.2 C2 (Cu Pillar with Solder Cap) Bumps; 2.3 Flip Chip Package Substrates; 2.3.1 Surface Laminar Circuit (SLC) Technology; 2.3.2 Integrated Thin-Film High-Density Organic Package (i-THOP); 2.3.3 Coreless Substrate; 2.3.4 Bump-on-Lead (BOL); 2.3.5 Embedded Trace Substrate (ETS); 2.4 Flip Chip Assembly; 2.4.1 Cu-to-Cu TCB Direct Bonding; 2.4.2 C4 Solder Mass Reflow; 2.4.3 C2 Solder Mass Reflow; 2.4.4 C2 TCB; 2.4.4.1 C2 TCB with Low Bonding Force; 2.4.4.2 C2 TCB with High Bonding Force. 2.5 Underfill/Reliability2.6 Post-assembly Underfill; 2.6.1 Capillary Underfill (CUF); 2.6.2 Molded Underfill (MUF); 2.6.3 Printed Underfill; 2.6.3.1 A New Stencil Design; 2.6.3.2 Test Chip; 2.6.3.3 Test Substrates; 2.6.3.4 Flip Chip Assemblies; 2.6.3.5 Stencil Designs; 2.6.3.6 Test Matrix; 2.6.3.7 Baking Substrates; 2.6.3.8 Printing Process; 2.6.3.9 Capillary Action and Curing; 2.6.3.10 Effects of Underfill Viscosity, Thermal Enhancement, and Multiple Prints; 2.6.3.11 Cross Sections; 2.6.3.12 Underfill Filler Density; 2.6.3.13 Shearing Test; 2.7 Preassembly Underfill. 2.8 Cu-Cu Direct Hybrid Bonding2.9 Flip Chip Technology Versus FOWLP; 2.10 Summary and Recommendations; References; 3 Fan-in Wafer-Level Packaging Versus FOWLP; 3.1 Introduction; 3.2 Fan-in Wafer-Level Packaging (WLP); 3.3 Wafer-Level Chip Scale Packages (WLCSPs); 3.4 WLCSP Test Vehicle; 3.4.1 The Chip; 3.4.2 The WLCSP; 3.4.3 WLCSP Key Process Steps; 3.5 PCB Assembly of the WLCSP; 3.6 Thermal Cycling Test of WLCSP-PCB Assembly; 3.6.1 Thermal Cycling Condition; 3.6.2 Crack Length Distribution of All Solder Joints; 3.6.3 Crack Propagation of the Corner Solder Joint.
• Publisher Details: Singapore : Springer
• Publication Date: 2018
• Extent: 1 online resource (xx, 303 pages), illustrations (some color)
• Subjects: 621.381/046; Chip scale packaging; TECHNOLOGY & ENGINEERING -- Mechanical; Chip scale packaging; Engineering; Circuits and Systems; Nanotechnology and Microengineering; Optical and Electronic Materials; Electronic books
• Languages: English
• ISBNs: 9789811088841; 9811088845
• Related ISBNs: 9789811088834; 9811088837
• Notes: Note: Includes bibliographical references.; Note: Online resource; title from PDF title page (SpringerLink, viewed April 10, 2018).
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.