Ambient communications and computer systems : RACCCS 2017 /: RACCCS 2017. (2018)
- Record Type:
- Book
- Title:
- Ambient communications and computer systems : RACCCS 2017 /: RACCCS 2017. (2018)
- Main Title:
- Ambient communications and computer systems : RACCCS 2017
- Other Titles:
- RACCCS 2017
- Further Information:
- Note: Gregorio Martinez Perez, Shailesh Tiwari, Munesh C. Trivedi, Krishn K. Mishra, editors.
- Editors:
- Martinez Pérez, Gregorio
Tiwari, Shailesh
Triv, Munesh C
Mishra, Krishn K - Other Names:
- RACCCS (Conference), 2nd
- Contents:
- Intro; Preface; Contents; About the Editors; Intelligent Hardware and Software Design; 1 Lion Algorithm: A Nature-Inspired Algorithm for Generation Rescheduling-Based Congestion Management; Abstract; 1 Introduction; 2 Literature Review; 3 Inspiration; 4 Model of Rescheduling-Based Congestion Management; 5 Steps of the Proposed Lion Algorithm; 6 Results and Discussion; 7 Conclusion; References; 2 A Dual-Coding Technique to Reduce Dynamic Power Dissipation in Deep Submicron (DSM) Technology; Abstract; 1 Introduction; 1.1 Existing Model of Bus; 2 Limitation of Existing Techniques. 3 Proposed Model3.1 Encoder; 3.2 Decoder; 4 Methodology; 5 Result and Analysis; 5.1 For 8 Bits; 5.2 For 16 Bits; 5.3 For 32 Bits; 5.4 For 64 Bits; 6 Conclusion; References; 3 Short-Term Solar Power Forecasting Using Random Vector Functional Link (RVFL) Network; Abstract; 1 Introduction; 2 Review of Related Neural Network Structures; 2.1 Single Shrouded Layer Feed-Forward Neural Network; 2.2 Random Weight Single Shrouded Layer Feed-Forward Neural Network; 2.3 SLFN with Direct Input-Output Connections (RVFL Network); 3 Data; 4 Experimental Setup; 4.1 Different Neural Network Configurations. 4.2 Error Measures4.3 Determination of the Number of Neurons in the Shrouded Layer; 5 Results; 6 Conclusion; References; 4 A CSA-Based Architecture of Vedic Multiplier for Complex Multiplication; Abstract; 1 Introduction; 2 Urdhva Tiryakbhyam Process and Complex Multiplication Architectures; 2.1 2 \times 2 Bit VedicIntro; Preface; Contents; About the Editors; Intelligent Hardware and Software Design; 1 Lion Algorithm: A Nature-Inspired Algorithm for Generation Rescheduling-Based Congestion Management; Abstract; 1 Introduction; 2 Literature Review; 3 Inspiration; 4 Model of Rescheduling-Based Congestion Management; 5 Steps of the Proposed Lion Algorithm; 6 Results and Discussion; 7 Conclusion; References; 2 A Dual-Coding Technique to Reduce Dynamic Power Dissipation in Deep Submicron (DSM) Technology; Abstract; 1 Introduction; 1.1 Existing Model of Bus; 2 Limitation of Existing Techniques. 3 Proposed Model3.1 Encoder; 3.2 Decoder; 4 Methodology; 5 Result and Analysis; 5.1 For 8 Bits; 5.2 For 16 Bits; 5.3 For 32 Bits; 5.4 For 64 Bits; 6 Conclusion; References; 3 Short-Term Solar Power Forecasting Using Random Vector Functional Link (RVFL) Network; Abstract; 1 Introduction; 2 Review of Related Neural Network Structures; 2.1 Single Shrouded Layer Feed-Forward Neural Network; 2.2 Random Weight Single Shrouded Layer Feed-Forward Neural Network; 2.3 SLFN with Direct Input-Output Connections (RVFL Network); 3 Data; 4 Experimental Setup; 4.1 Different Neural Network Configurations. 4.2 Error Measures4.3 Determination of the Number of Neurons in the Shrouded Layer; 5 Results; 6 Conclusion; References; 4 A CSA-Based Architecture of Vedic Multiplier for Complex Multiplication; Abstract; 1 Introduction; 2 Urdhva Tiryakbhyam Process and Complex Multiplication Architectures; 2.1 2 \times 2 Bit Vedic Multiplier; 2.2 Complex Multiplication Process Using Vedic Multiplier; 3 Proposed Vedic Multiplier Architecture; 3.1 Binary to Excess-1 Code Converter (BEC-1); 3.2 Multi-Operand Carry-Save Adder (CSA); 4 Implementation Results and Performance Evaluation; 5 Conclusion; References. 5 Design and Analysis of 8-Bit Carry Look-Ahead Adder Using CMOS and ECRL TechnologyAbstract; 1 Introduction; 2 Background Details and Related Work; 3 Proposed Approach; 4 Experimental Setup and Results; 4.1 Implementation of 8-Bit CLA Using CMOS Logic; 4.2 Implementation of 8-Bit CLA Using ECRL Logic; 4.3 Result and Discussion; 5 Conclusions; References; 6 Enhancement of Microstrip Patch Antenna Parameters Using Defective Ground Structure; Abstract; 1 Introduction; 2 Background Details and Related Work; 3 Proposed Approach; 4 Experimental Setup and Results; 5 Conclusion; References. 7 Adaptive Neural Type II Fuzzy Logic-Based Speed Control of Induction Motor DriveAbstract; 1 Introduction; 2 Vector-Controlled Induction Motor; 3 Speed Control Schemes; 3.1 Fuzzy Type II Logic; 3.2 Adaptive Neural Fuzzy Type II Logic; 4 Simulation Results; 5 Conclusions; Appendix; References; 8 Hybrid Methodology for Optimal Allocation of Synchronous Generator-Based DG; Abstract; 1 Introduction; 2 Voltage-Dependent Loads; 3 Problem Formulation; 3.1 Objective Function; 3.2 Limiting Search Space; 4 Optimum Allocation of Synchronous Generator-Based DG; 4.1 Optimum Power Factor of DG. … (more)
- Publisher Details:
- Singapore : Springer
- Publication Date:
- 2018
- Extent:
- 1 online resource
- Subjects:
- 621.382
Telecommunication systems -- Congresses
Ambient intelligence -- Congresses
Computer networks -- Congresses
TECHNOLOGY & ENGINEERING -- Mechanical
Ambient intelligence
Computer networks
Telecommunication systems
Data Mining and Knowledge Discovery
Electronic books
Conference papers and proceedings - Languages:
- English
- ISBNs:
- 9789811073861
9811073864 - Related ISBNs:
- 9789811073854
9811073856 - Notes:
- Note: Online resource; title from PDF title page (SpringerLink, viewed March 26, 2018).
- Access Rights:
- Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
- Access Usage:
- Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.
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- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD.DS.406649
- Ingest File:
- 02_476.xml