Normally-off computing. (2017)

• Record Type: Book
• Further Information: Note: Takashi Nakada, Hiroshi Nakamura, editors.
• Editors: Nakada, Takashi; Nakamura, Hiroshi
• Contents: Preface; Contents; 1 Introduction; 1.1 Background; 1.1.1 Sustainable Society; 1.1.2 Power Management; 1.1.3 Emerging Technology: Non-volatile Memory; 1.2 Normally-Off Computing; 1.2.1 Management Granularity; 1.3 Expectation on Normally-Off Computing; 1.4 Organization of This Book; References; 2 Low-Power Circuit Technologies; 2.1 Introduction; 2.2 Basics of Low Power Techniques; 2.2.1 Heterogeneous Hardware; 2.2.2 DVFS; 2.2.3 Dynamic Power Management; 2.2.4 Sleep Mode; 2.2.5 Fine-Grained Power Gating; 2.3 Energy/Performance Trade-Off; 2.3.1 Transition Energy and BETs. 2.3.2 Access Energy of NVRAM and BET2.4 Summary; References; 3 Non-volatile Memories; 3.1 Introduction; 3.2 Variety of NVRAM; 3.2.1 STT-MRAM; 3.2.2 ReRAM; 3.2.3 PCRAM; 3.2.4 FeRAM; 3.2.5 NOR Flash; 3.3 Summary; References; 4 Normally-Off Computing; 4.1 Introduction; 4.2 Device Technologies; 4.3 Architectural Technologies; 4.3.1 Memory Hierarchy; 4.3.2 Heterogeneous Hardware; 4.4 Activity Control Technologies; 4.5 Normally-Off Computing Design Methodology; 5 Technologies for Realizing Normally-Off Computing; 5.1 Overview; 5.2 Logic; 5.2.1 Non-volatile Logic; 5.3 Memory/Cache. 5.3.1 Embedded STT-MRAM for High-Performance Processors5.4 Micro Controller; 5.4.1 Overview of sensor node; 5.4.2 Low-power technologies; 5.5 Scheduling; 5.5.1 Introduction; 5.5.2 Scheduling for Multi-core System; 5.5.3 System Description and Constraint Modeling; 5.5.4 Optimal Scheduling; 5.6 Data Management; 5.6.1 Introduction; 5.6.2 Motivating Example; 5.6.3 Data-Aware Power Management; 5.7 Conclusion; References; 6 Research and Development of Normally-Off Computing -- NEDO Project; 6.1 Overview; 6.2 Healthcare; 6.2.1 Background; 6.2.2 System Description and Normally-Off ECG-SoC Architecture. 6.2.3 Noise Tolerant and Low-Power ECG Sensing Block6.2.4 Implementation Result; 6.2.5 Conclusion; 6.3 Mobile Information Device (MID); 6.3.1 Memory Hierarchy with STT-MRAM for MID; 6.3.2 How to Reduce Power for Each Low-Power Processor State with STT-MRAM-Based Cache; 6.4 Sensor Node for Social Infrastructure; 6.4.1 Sensor Network System for Smart City Application; References; 7 Related Research & Development; 7.1 Overview; 7.2 Germany; 7.3 The U.S.A; 7.4 Japan; Reference; 8 Conclusion.
• Publisher Details: Tokyo, Japan : Springer
• Publication Date: 2017
• Extent: 1 online resource (vii, 136 pages), illustrations (some color)
• Subjects: 621.39/5; Computers -- Energy consumption; Computers -- Power supply; Computer engineering; Memory management (Computer science); COMPUTERS -- Computer Engineering; Computer engineering; Computers -- Power supply; Memory management (Computer science); Computer Science; Memory Structures; Electrical Engineering; Renewable and Green Energy; Electronic books
• Languages: English
• ISBNs: 9784431565055; 4431565051
• Related ISBNs: 9784431565031; 4431565035
• Notes: Note: Includes bibliographical references.; Note: Online resource; title from PDF title page (SpringerLink, viewed January 27, 2017).
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.