Network and parallel computing : 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29-December 1, 2018, Proceedings /: 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29-December 1, 2018, Proceedings. (2018)
- Record Type:
- Book
- Title:
- Network and parallel computing : 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29-December 1, 2018, Proceedings /: 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29-December 1, 2018, Proceedings. (2018)
- Main Title:
- Network and parallel computing : 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29-December 1, 2018, Proceedings
- Other Titles:
- NPC 2018
- Further Information:
- Note: Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero (eds.).
- Editors:
- Zhang, Feng
Zhai, Jidong
Snir, Marc
Jin, Hai, 1966-
Kasahara, Hironori
Valero, Mateo - Other Names:
- NPC (Conference), 15th
- Contents:
- CNLoc: Channel State Information Assisted Indoor WLAN Localization Using Nomadic Access Points -- ALOR: Adaptive Layout Optimization of Raft Groups for Heterogeneous Distributed Key-Value Stores -- STrieGD: A Sampling Trie Indexed Compression Algorithm for Large-Scale Gene Data -- On Retargeting the AI Programming Framework to New Hardwares -- An Efficient Method For Determining Full Point-to-point Latency Of Arbitrary Indirect HPC Networks -- KT-Store: A Key-Order and Write-Order Hybrid Key-Value Store with High Write and Range-query Performance -- GRAM: A GPU-based Property Graph Traversal and Query for HPC Rich Metadata Management -- GPU-Accelerated Clique Tree Propagation for Pouch Latent Tree Models -- HPC-SFI: System-level Fault Injection for High Performance Computing Systems -- Data Fine-pruning: A Simple Way to Accelerate Neural Network Training -- Balancing the QOS and Security in Dijkstra Algorithm by SDN Technology -- Labeled Network Stack: A Co-Designed Stack for Low Tail-Latency and High Concurrency in Datacenter Services -- A Deep Learning Approach for Network Anomaly Detection based on AMF-LSTM -- FSObserver: A Performance Measurement and Monitoring Tool for Distributed Storage Systems -- vGrouper: Optimizing the Performance of Parallel Jobs in Xen by Increasing Synchronous Execution of Virtual Machines -- Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms -- A Fine-grained Performance Bottleneck Analysis Method for HDFS --CNLoc: Channel State Information Assisted Indoor WLAN Localization Using Nomadic Access Points -- ALOR: Adaptive Layout Optimization of Raft Groups for Heterogeneous Distributed Key-Value Stores -- STrieGD: A Sampling Trie Indexed Compression Algorithm for Large-Scale Gene Data -- On Retargeting the AI Programming Framework to New Hardwares -- An Efficient Method For Determining Full Point-to-point Latency Of Arbitrary Indirect HPC Networks -- KT-Store: A Key-Order and Write-Order Hybrid Key-Value Store with High Write and Range-query Performance -- GRAM: A GPU-based Property Graph Traversal and Query for HPC Rich Metadata Management -- GPU-Accelerated Clique Tree Propagation for Pouch Latent Tree Models -- HPC-SFI: System-level Fault Injection for High Performance Computing Systems -- Data Fine-pruning: A Simple Way to Accelerate Neural Network Training -- Balancing the QOS and Security in Dijkstra Algorithm by SDN Technology -- Labeled Network Stack: A Co-Designed Stack for Low Tail-Latency and High Concurrency in Datacenter Services -- A Deep Learning Approach for Network Anomaly Detection based on AMF-LSTM -- FSObserver: A Performance Measurement and Monitoring Tool for Distributed Storage Systems -- vGrouper: Optimizing the Performance of Parallel Jobs in Xen by Increasing Synchronous Execution of Virtual Machines -- Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms -- A Fine-grained Performance Bottleneck Analysis Method for HDFS -- Mimir+ : An Optimized Framework of MapReduce on Heterogeneous High-Performance Computing System -- DLIR: An Intermediate Representation for Deep Learning Processors -- GPU Memory Management Solution Supporting Incomplete Pages -- Leveraging Subgraph Extraction for Performance Portable Programming Frameworks on DL Accelerators -- An Intelligent Parking Scheduling Algorithm based on Traffic and Driver Behavior Predictions. . … (more)
- Publisher Details:
- Cham : Springer
- Publication Date:
- 2018
- Extent:
- 1 online resource (XII, 192 pages. 115 illustrations, 73 illustrations in color.)
- Subjects:
- 004.6/185
Parallel processing (Electronic computers) -- Congresses
Computer networks -- Congresses
Parallel computers -- Congresses
Electronic books - Languages:
- English
- ISBNs:
- 9783030056773
3030056775 - Related ISBNs:
- 9783030056766
- Notes:
- Note: Online resource; title from PDF title page (SpringerLink, viewed January 9, 2019).
- Access Rights:
- Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
- Access Usage:
- Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD.DS.382014
- Ingest File:
- 02_368.xml