Reconfigurable system design and verification. (2018)

• Record Type: Book
• Further Information: Note: Pao-Ann Hsiung, Marco D. Santambrogio, Chun-Hsian Huang.
• Other Names: Hsiung, Pao-Ann; Santambrogio, Marco D (Marco Domenico); Huang, Chun-Hsian
• Contents: <span style="font-size: 10pt;">Introductionto Reconfigurable Computing <span style="font-size: 10pt;">Why Reconfigurable Computing? <span style="font-size: 10pt;">What is Reconfiurable Computing? <span style="font-size: 10pt;">From Codesign to Reconfiguration <span style="font-size: 10pt;">Reconfiguration Technology <span style="font-size: 10pt;">Reconfiguration Tools and Platforms <span style="font-size: 10pt;">Design and Verification Methodologies <span style="font-size: 10pt;">Application Examples <span style="font-size: 10pt;"> <span style="font-size: 10pt;">FPGATechnology and Dynamic Reconfiguration <span style="font-size: 10pt;">FPGA Overview <span style="font-size: 10pt;">The Configuration Bitstream <span style="font-size: 10pt;">2.3 FPGA Families and Models <span style="font-size: 10pt;">2.4 Configuration Conventions and File Formats <span style="font-size: 10pt;">A Bird's Eye View on Reconfigurable Systems <span style="font-size: 10pt;">Reconfiguration Characterization <span style="font-size: 10pt;"> <b style=""><span style="font-size: 10pt;">ReconfigurableHardware Design <span style="font-size: 10pt;">Model <span style="font-size: 10pt;">Partitioning for Reconfigurable Architectures <span style="font-size: 10pt;">Scheduling Techniques <span style="font-size: 10pt;"> <span style="font-size: 10pt;">OperatingSystem for Reconfigurable Systems <span style="font-size: 10pt;">Motivation for OS4RS <span style="font-size: 10pt;">Requirements for OS4RS <span style="font-size: 10pt;">Layered Architecture for OS4RS <p class="MsoNormal" style=""><span style="font-size: 10pt;">OS4RS Examples <span style="font-size: 10pt;"> <span style="font-size: 10pt;">DynamicReconfigurable Systems Design Flows <span style="font-size: 10pt;">System Design Flows <span style="font-size: 10pt;">Reconfigurable System Design Flow: Structure and Implementation <span style="font-size: 10pt;">The hardware Side of the Ddesign Flow <span style="font-size: 10pt;"> <span style="font-size: 10pt;">ReconfigurableSystem Verification <span style="font-size: 10pt;">System-Level Verification Techniques <span style="font-size: 10pt;">Hardware-Software Coverification <span style="font-size: 10pt;">Reconfigurable System Simulation Frameworks <span style="font-size: 10pt;">Perfecto Framework <span style="font-size: 10pt;"> <span style="font-size: 10pt;">DynamicallyPartially Reconfigurable System Design Implementation <span style="font-size: 10pt;">Partial Reconfiguration on Xilinx Virtex Family FPGAs <span style="font-size: 10pt;">Early Access Partial Reconfiguration Design Flow <span style="font-size: 10pt;">Creating Partially Reconfigurable Hardware Design <span style="font-size: 10pt;">Software-Controlled Partially Reconfigurable Design <span style="font-size: 10pt;">Operating System for Reconfigurable Systems <span style="font-size: 10pt;">References
• Publisher Details: Place of publication not identified : CRC Press
• Publication Date: 2018
• Extent: 1 online resource (268 pages), (22 illustrations)
• Subjects: 004.21; Embedded computer systems; System design; Computer systems -- Verification
• Languages: English
• ISBNs: 9781351834926; 1351834924
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.