Parallel sparse direct solver for integrated circuit simulation. (2017)

• Record Type: Book
• Further Information: Note: Xiaoming Chen, Yu Wang, Huazhong Yang.
• Authors: Chen, Xiaoming; Wang, Yu; Yang, Huazhong
• Contents: Preface; Contents; 1 Introduction; 1.1 Circuit Simulation; 1.1.1 Mathematical Formulation; 1.1.2 LU Factorization; 1.1.3 Simulation Flow; 1.2 Challenges of Parallel Circuit Simulation; 1.2.1 Device Model Evaluation; 1.2.2 Sparse Direct Solver; 1.2.3 Theoretical Speedup; 1.3 Focus of This Book; References; 2 Related Work; 2.1 Direct Parallel Methods; 2.1.1 Parallel Direct Matrix Solutions; 2.1.2 Parallel Iterative Matrix Solutions; 2.2 Domain Decomposition; 2.2.1 Parallel BBD-Form Matrix Solutions; 2.2.2 Parallel Multilevel Newton Methods; 2.2.3 Parallel Schwarz Methods. 2.2.4 Parallel Relaxation Methods2.3 Parallel Time-Domain Simulation; 2.3.1 Parallel Numerical Integration Algorithms; 2.3.2 Parallel Multi-Algorithm Simulation; 2.3.3 Time-Domain Partitioning; 2.3.4 Matrix Exponential Methods; 2.4 Hardware Acceleration Techniques; 2.4.1 GPU Acceleration; 2.4.2 FPGA Acceleration; References; 3 Overall Solver Flow; 3.1 Overall Flow; 3.2 Pre-analysis; 3.2.1 Zero-Free Permutation/Static Pivoting; 3.2.2 Matrix Ordering; 3.2.3 Symbolic Factorization; 3.3 Numerical Full Factorization; 3.3.1 Symbolic Prediction; 3.3.2 Numerical Update; 3.3.3 Partial Pivoting. 3.3.4 Pruning3.4 Numerical Re-factorization; 3.4.1 Factorization Method Selection; 3.5 Right-Hand-Solving; 3.5.1 Forward/Backward Substitutions; 3.5.2 Iterative Refinement; References; 4 Parallel Sparse Left-Looking Algorithm; 4.1 Parallel Full Factorization; 4.1.1 Data Dependence Representation; 4.1.2 Task Scheduling; 4.1.3 Algorithm Flow; 4.1.4 Implementation Details; 4.2 Parallel Re-factorization; 4.2.1 Data Dependence Representation; 4.2.2 Task Scheduling; 4.2.3 Algorithm Flow; 4.2.4 Implementation Details; References; 5 Improvement Techniques; 5.1 Map Algorithm; 5.1.1 Motivation. 5.1.2 Map Definition and Construction5.1.3 Sequential Map Re-factorization; 5.1.4 Parallel Map Re-factorization; 5.2 Supernodal Algorithm; 5.2.1 Motivation; 5.2.2 Supernode Definition and Storage; 5.2.3 Supernodal Full Factorization; 5.2.4 Supernodal Re-factorization; 5.3 Fast Full Factorization; 5.3.1 Motivation and Pivoting Reduction; 5.3.2 Sequential Fast Full Factorization; 5.3.3 Parallel Fast Full Factorization; References; 6 Test Results; 6.1 Experimental Setup; 6.2 Performance Metric; 6.2.1 Speedups; 6.2.2 Performance Profile; 6.3 Results of Benchmark Test. 6.3.1 Comparison of Different Algorithms6.3.2 Relative Speedups; 6.3.3 Speedups; 6.3.4 Other Comparisons; 6.4 Results of Simulation Test; References; 7 Performance Model; 7.1 DAG-Based Performance Model; 7.2 Results and Analysis; 7.2.1 Theoretical Maximum Relative Speedup; 7.2.2 Predicted Relative Speedup; 7.2.3 Bottleneck Analysis; 8 Conclusions; Reference; Index.
• Publisher Details: Cham, Switzerland : Springer
• Publication Date: 2017
• Extent: 1 online resource
• Subjects: 621.39/5; Engineering; Integrated circuits -- Computer simulation; Integrated circuits -- Design and construction; TECHNOLOGY & ENGINEERING -- Mechanical; Integrated circuits -- Computer simulation; Integrated circuits -- Design and construction; Engineering; Circuits and Systems; Processor Architectures; Electronics and Microelectronics, Instrumentation; Computers -- Systems Architecture -- General; Technology & Engineering -- Electronics -- General; Computer architecture & logic design; Electronics engineering; Systems engineering; Computer science; Electronics; Technology & Engineering -- Electronics -- Circuits -- General; Circuits & components; Electronic books
• Languages: English
• ISBNs: 9783319534299; 3319534297
• Related ISBNs: 9783319534282; 3319534289
• Notes: Note: Includes bibliographical references and index.; Note: Online resource; title from PDF title page (SpringerLink, viewed February 21, 2017).
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
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