Thread and data mapping for multicore systems : improving communication and memory accesses /: improving communication and memory accesses. ([2018])
- Record Type:
- Book
- Title:
- Thread and data mapping for multicore systems : improving communication and memory accesses /: improving communication and memory accesses. ([2018])
- Main Title:
- Thread and data mapping for multicore systems : improving communication and memory accesses
- Further Information:
- Note: Eduardo H.M. Cruz, Matthias Diener, Philippe O.A. Navaux.
- Authors:
- Cruz, Eduardo H. M
Navaux, Philippe O. A - Other Names:
- Diener, Matthias
- Contents:
- Intro; Preface; Contents; Acronyms; 1 Introduction; 1.1 Improving Memory Locality with Sharing-Aware Mapping; 1.2 Monitoring Memory Accesses for Sharing-Aware Mapping; 1.3 Organization of the Text; 2 Sharing-Aware Mapping and Parallel Architectures; 2.1 Understanding Memory Locality in Shared Memory Architectures; 2.1.1 Lower Latency When Sharing Data; 2.1.2 Reduction of the Impact of Cache Coherence Protocols; 2.1.3 Reduction of Cache Misses; 2.1.3.1 Capacity Misses; 2.1.3.2 Invalidation Misses; 2.1.3.3 Replication Misses; 2.1.4 Reduction of Memory Accesses to Remote NUMA Nodes 2.1.5 Better Usage of Interconnections2.2 Example of Shared Memory Architectures Affected by Memory Locality; 2.2.1 Intel Harpertown; 2.2.2 Intel Nehalem/Sandy Bridge; 2.2.3 AMD Abu Dhabi; 2.2.4 Intel Montecito/SGI NUMAlink; 2.3 Locality in the Context of Network Clusters and Grids; 3 Sharing-Aware Mapping and Parallel Applications; 3.1 Parallel Applications and Sharing-Aware Thread Mapping; 3.1.1 Considerations About the Sharing Pattern; 3.1.1.1 Dimension of the Sharing Pattern; 3.1.1.2 Granularity of the Sharing Pattern (Memory Block Size) 3.1.1.3 Data Structure Used to Store the Thread Sharers of a Memory Block3.1.1.4 History of the Sharing Pattern; 3.1.2 Sharing Patterns of Parallel Applications; 3.1.3 Varying the Granularity of the Sharing Pattern; 3.1.4 Varying the Number of Sharers of the Sharing Pattern; 3.2 Parallel Applications and Sharing-Aware Data Mapping; 3.2.1 Parameters that InfluenceIntro; Preface; Contents; Acronyms; 1 Introduction; 1.1 Improving Memory Locality with Sharing-Aware Mapping; 1.2 Monitoring Memory Accesses for Sharing-Aware Mapping; 1.3 Organization of the Text; 2 Sharing-Aware Mapping and Parallel Architectures; 2.1 Understanding Memory Locality in Shared Memory Architectures; 2.1.1 Lower Latency When Sharing Data; 2.1.2 Reduction of the Impact of Cache Coherence Protocols; 2.1.3 Reduction of Cache Misses; 2.1.3.1 Capacity Misses; 2.1.3.2 Invalidation Misses; 2.1.3.3 Replication Misses; 2.1.4 Reduction of Memory Accesses to Remote NUMA Nodes 2.1.5 Better Usage of Interconnections2.2 Example of Shared Memory Architectures Affected by Memory Locality; 2.2.1 Intel Harpertown; 2.2.2 Intel Nehalem/Sandy Bridge; 2.2.3 AMD Abu Dhabi; 2.2.4 Intel Montecito/SGI NUMAlink; 2.3 Locality in the Context of Network Clusters and Grids; 3 Sharing-Aware Mapping and Parallel Applications; 3.1 Parallel Applications and Sharing-Aware Thread Mapping; 3.1.1 Considerations About the Sharing Pattern; 3.1.1.1 Dimension of the Sharing Pattern; 3.1.1.2 Granularity of the Sharing Pattern (Memory Block Size) 3.1.1.3 Data Structure Used to Store the Thread Sharers of a Memory Block3.1.1.4 History of the Sharing Pattern; 3.1.2 Sharing Patterns of Parallel Applications; 3.1.3 Varying the Granularity of the Sharing Pattern; 3.1.4 Varying the Number of Sharers of the Sharing Pattern; 3.2 Parallel Applications and Sharing-Aware Data Mapping; 3.2.1 Parameters that Influence Sharing-Aware Data Mapping; 3.2.1.1 Influence of the Memory Page Size; 3.2.1.2 Influence of Thread Mapping; 3.2.2 Analyzing the Data Mapping Potential of Parallel Applications 3.2.3 Influence of the Page Size on Sharing-Aware Data Mapping3.2.4 Influence of Thread Mapping on Sharing-Aware Data Mapping; 4 State-of-the-Art Sharing-Aware Mapping Methods; 4.1 Sharing-Aware Static Mapping; 4.1.1 Static Thread Mapping; 4.1.2 Static Data Mapping; 4.1.3 Combined Static Thread and Data Mapping; 4.2 Sharing-Aware Online Mapping; 4.2.1 Online Thread Mapping; 4.2.2 Online Data Mapping; 4.2.3 Combined Online Thread and Data Mapping; 4.3 Discussion on Sharing-Aware Mapping and the State-of-Art; 4.4 Improving Performance with Sharing-Aware Mapping; 4.4.1 Mapping Mechanisms 4.4.1.1 Source Code Changes4.4.1.2 Offline Profiling at the User Level; 4.4.1.3 Runtime Options; 4.4.1.4 Online Profiling at the System Level; 4.4.2 Methodology of the Experiments; 4.4.3 Results; 5 Conclusions; References … (more)
- Publisher Details:
- Cham, Switzerland : Springer
- Publication Date:
- 2018
- Copyright Date:
- 2018
- Extent:
- 1 online resource (ix, 54 pages), illustrations
- Subjects:
- 005.2/75
Computer science
Parallel programming (Computer science)
Multiprocessors
Threads (Computer programs)
Digital mapping
COMPUTERS / Programming / Parallel
Digital mapping
Multiprocessors
Parallel programming (Computer science)
Threads (Computer programs)
Computer Science
Computer Hardware
Software Engineering/Programming and Operating Systems
Computers -- Software Development & Engineering -- General
Software Engineering
Computer hardware
Software engineering
Computers -- Hardware -- General
Computer hardware
Electronic books - Languages:
- English
- ISBNs:
- 9783319910741
3319910744 - Related ISBNs:
- 9783319910734
3319910736 - Notes:
- Note: Includes bibliographical references.
Note: Online resource; title from PDF title page (EBSCO, viewed July 12, 2018). - Access Rights:
- Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
- Access Usage:
- Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD.DS.348106
- Ingest File:
- 01_302.xml