Designing with Xilinx FPGAs : using Vivado /: using Vivado. ([2017])

• Record Type: Book
• Further Information: Note: Sanjay Churiwala, editor.
• Editors: Churiwala, Sanjay
• Contents: State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.
• Publisher Details: Switzerland : Springer
• Publication Date: 2017
• Extent: 1 online resource (x, 260 pages)
• Subjects: 621.39/5; Engineering; Field programmable gate arrays; Computer-aided design; TECHNOLOGY & ENGINEERING / Mechanical; Computer-aided design; Field programmable gate arrays; Computers -- Systems Architecture -- General; Technology & Engineering -- Electronics -- General; Computer architecture & logic design; Electronics engineering; Systems engineering; Computer science; Electronics; Technology & Engineering -- Electronics -- Circuits -- General; Circuits & components; Electronic books
• Languages: English
• ISBNs: 9783319424385; 3319424386
• Related ISBNs: 9783319424378; 3319424378
• Notes: Note: Includes bibliographical references and index.; Note: Print version record.
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.