Test generation of crosstalk delay faults in VLSI circuits. ([2019])

• Record Type: Book
• Further Information: Note: S. Jayanthy, M.C. Bhuvaneswari.
• Authors: Jayanthy, S; Bhuvaneswari, M. C
• Contents: Please see attached.
• Publisher Details: Singapore : Springer
• Publication Date: 2019
• Extent: 1 online resource (xi, 156 pages), illustrations (some color)
• Subjects: 621.39/5; Engineering; Integrated circuits -- Very large scale integration -- Testing; Crosstalk; TECHNOLOGY & ENGINEERING / Mechanical; Computers -- Systems Architecture -- General; Computers -- Hardware -- General; Computers -- Logic Design; Algorithms & data structures; Systems analysis & design; Computer architecture & logic design; Systems engineering; Microprogramming; Operating systems (Computers); Logic design; Technology & Engineering -- Electronics -- Circuits -- General; Circuits & components; Electronic books
• Languages: English
• ISBNs: 9789811324932
• Related ISBNs: 981132493X; 9789811324925
• Notes: Note: Includes bibliographical references.; Note: Online resource; title from PDF title page (SpringerLink, viewed September 25, 2018).
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.