Principles and structures of FPGAs. (c2018)

• Record Type: Book
• Further Information: Note: Hideharu Amano, editor.
• Editors: Amano, Hideharu
• Contents: Intro; Preface; Contents; Contributors; 1 Basic Knowledge to Understand FPGAs; 1.1 Logic Circuits; 1.1.1 Logic Algebra; 1.1.2 Logic Equation; 1.1.3 Truth Table; 1.1.4 Combinational Circuits; 1.1.5 Sequential Circuits; 1.2 Synchronous Logic Design; 1.2.1 Flip-Flop; 1.2.2 Setup Time and Hold Time; 1.2.3 Timing Analysis; 1.2.4 Single-Clock Synchronous Circuits; 1.3 Position and History of FPGAs; 1.3.1 The Position of FPGA; References; 2 What Is an FPGA?; 2.1 Components of an FPGA; 2.2 Programming Technology; 2.2.1 Flash Memory; 2.3 Antifuse Technology; 2.3.1 Static Memory Technology 2.3.2 Summary of Programming Technology2.4 Logic Circuit Representation of FPGA; 2.4.1 Circuit Implementation on FPGA; 2.4.2 Logical Expression by Product Term; 2.4.3 Logical Expression by Lookup Table; 2.4.4 Structure of Lookup Table; 2.4.5 Logical Expression by Other Methods; References; 3 FPGA Structure; 3.1 Logic Block; 3.1.1 Performance Trade-Off of Lookup Tables; 3.1.2 Dedicated Carry Logic; 3.2 Logic Cluster; 3.3 Adaptive LUT; 3.3.1 Altera Stratix II; 3.3.2 Xilinx Virtex 5; 3.4 Routing Part; 3.4.1 Global Routing Architecture; 3.4.2 Detailed Routing Architecture 3.4.3 Wire Segment Length3.4.4 Structure of Routing Switch; 3.5 Switch Block; 3.5.1 Switch Block Topology; 3.5.2 Multiplexer Structure; 3.6 Connection Block; 3.7 I/O Block; 3.8 DSP Block; 3.8.1 Example Structure of a DSP Block; 3.8.2 Arithmetic Granularity; 3.8.3 Usage of DSP Blocks; 3.9 Hard Macros; 3.9.1 Interface Circuits as Hard Macros; 3.9.2 Hard-Core Processors; 3.10 Embedded Memory; 3.10.1 Memory Blocks as Hard Macros; 3.10.2 Memory Using LUTs in Logic Blocks; 3.10.3 Usage of Embedded Memory; 3.11 Configuration Chain; 3.11.1 Memory Technologies for Configuration; 3.11.2 JTAG Interface 3.12 PLL and DLL3.12.1 Basic Structure and Operating Principle of PLL; 3.12.2 Typical PLL Block; 3.12.3 Flexibility and Restriction of PLL Blocks; 3.12.4 Lock Output; 3.12.5 DLL; References; 4 Design Flow and Design Tools; 4.1 Design Flow; 4.2 Design Flow by HDL; 4.2.1 Registration of Project; 4.2.2 Logic Synthesis and Technology Mapping; 4.2.3 RTL Simulation; 4.2.4 Place and Route; 4.2.5 Programming; 4.2.6 Verification and Debugging on Actual Device; 4.2.7 Optimization; 4.3 HLS Design; 4.3.1 Behavioral Description; 4.3.2 Behavior Level Simulation; 4.3.3 Behavioral Synthesis 4.3.4 Evaluation and Optimization4.3.5 Connection with RTL; 4.4 IP-Based Design; 4.4.1 IP and Its Generator; 4.4.2 Use of IP and Its Integration Tool; 4.4.3 Support Tool for Building IP; 4.5 Design with Processor; 4.5.1 Hard-Core Processor and Soft-Core Processor; 4.5.2 Building Processor System; 4.5.3 Software Development Environment; 4.5.4 Integration and Operation of Software and Hardware; References; 5 Design Methodology; 5.1 FPGA Design Flow; 5.2 Technology Mapping; 5.3 Clustering; 5.4 Place and Route; 5.5 Low Power Design Tools; 5.5.1 Emap: Low Power Consumption Mapping Tool
• Publisher Details: Singapore : Springer
• Publication Date: 2018
• Copyright Date: 2018
• Extent: 1 online resource
• Subjects: 621.39/5; Computer science; Field programmable gate arrays; TECHNOLOGY & ENGINEERING / Mechanical; Circuits & components; Electronics engineering; Computer architecture & logic design; Technology & Engineering -- Electronics -- Circuits -- General; Technology & Engineering -- Electronics -- General; Logic design; Systems engineering; Electronics; Computers -- Logic Design; Electronic books
• Languages: English
• ISBNs: 9789811308246; 9811308241
• Related ISBNs: 9789811308239; 9811308233
• Notes: Note: Online resource; title from PDF title page (EBSCO, viewed September 18, 2018)
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.