Multicore DSP : from algorithms to real-time implementation on the TMS320C66x SoC /: from algorithms to real-time implementation on the TMS320C66x SoC. (2018)

• Record Type: Book
• Further Information: Note: Naim Dahnoun.
• Authors: Dahnoun, Naim
• Contents: Preface xviii Acknowledgements xxi Foreword xxii About the Companion Website xxiii 1 Introduction to DSP 1 1.1 Introduction 1 1.2 Multicore processors 3 1.2.1 Can any algorithm benefit from a multicore processor? 3 1.2.2 How many cores do I need for my application? 5 1.3 Key applications of high-performance multicore devices 6 1.4 FPGAs, Multicore DSPs, GPUs and Multicore CPUs 8 1.5 Challenges faced for programming a multicore processor 9 1.6 Texas Instruments DSP roadmap 10 1.7 Conclusion 11 References 12 2 The TMS320C66x architecture overview 14 2.1 Overview 14 2.2 The CPU 15 2.2.1 Cross paths 16 2.2.1.1 Data cross paths 17 2.2.1.2 Address cross paths 18 2.2.2 Register file A and file B 20 2.2.2.1 Operands 20 2.2.3 Functional units 21 2.2.3.1 Condition registers 21 2.2.3.2 .L units 22 2.2.3.3 .M units 22 2.2.3.4 .S units 23 2.2.3.5 .D units 23 2.3 Single instruction, multiple data (SIMD) instructions 24 2.3.1 Control registers 24 2.4 The KeyStone memory 24 2.4.1 Using the internal memory 27 2.4.2 Memory protection and extension 29 2.4.3 Memory throughput 29 2.5 Peripherals 30 2.5.1 Navigator 32 2.5.2 Enhanced Direct Memory Access (EDMA) Controller 32 2.5.3 Universal Asynchronous Receiver/Transmitter (UART) 32 2.5.4 General purpose input–output (GPIO) 32 2.5.5 Internal timers 32 2.6 Conclusion 33 References 33 3 Software development tools and the TMS320C6678 EVM 35 3.1 Introduction 35 3.2 Software development tools 37 3.2.1 Compiler 38 3.2.2 Assembler 39 3.2.3 Linker 40 3.2.3.1 Linker command file 40 3.2.4 Compile, assemble and link 42 3.2.5 Using the Real-Time Software Components (RTSC) tools 42 3.2.5.1 Platform update using the XDCtools 42 3.2.6 KeyStone Multicore Software Development Kit 47 3.3 Hardware development tools 47 3.3.1 EVM features 47 3.4 Laboratory experiments based on the C6678 EVM: introduction to Code Composer Studio (CCS) 51 3.4.1 Software and hardware requirements 51 3.4.1.1 Key features 52 3.4.1.2 Download sites 53 3.4.2 Laboratory experiments with the CCS6 53 3.4.2.1 Introduction to CCS 55 3.4.2.2 Implementation of a DOTP algorithm 63 3.4.3 Profiling using the clock 65 3.4.4 Considerations when measuring time 67 3.5 Loading different applications to different cores 67 3.6 Conclusion 72 References 72 4 Numerical issues 74 4.1 Introduction 74 4.2 Fixed- and floating-point representations 75 4.2.1 Fixed-point arithmetic 76 4.2.1.1 Unsigned integer 76 4.2.1.2 Signed integer 77 4.2.1.3 Fractional numbers 77 4.2.2 Floating-point arithmetic 78 4.2.2.1 Special numbers for the 32-bit and 64-bit floating-point formats 81 4.3 Dynamic range and accuracy 82 4.4 Laboratory exercise 83 4.5 Conclusion 85 References 85 5 Software optimisation 86 5.1 Introduction 86 5.2 Hindrance to software scalability for a multicore processor 88 5.3 Single-core code optimisation procedure 88 5.3.1 The C compiler options 90 5.4 Interfacing C with intrinsics, linear assembly and assembly 91 5.4.1 Intrinsics 91 5.4.2 Interfacing C and assembly 92 5.5 Assembly optimisation 97 5.5.1 Parallel instructions 98 5.5.2 Removing the NOPs 99 5.5.3 Loop unrolling 99 5.5.4 Double-Word Access 100 5.5.5 Optimisation summary 100 5.6 Software pipelining 101 5.6.1 Software-pipelining procedure 105 5.6.1.1 Writing linear assembly code 105 5.6.1.2 Creating a dependency graph 105 5.6.1.3 Resource allocation 108 5.6.1.4 Scheduling table 108 5.6.1.5 Generating assembly code 109 5.7 Linear assembly 111 5.7.1 Hand optimisation of the dotp function using linear assembly 112 5.8 Avoiding memory banks 118 5.9 Optimisation using the tools 118 5.10 Laboratory experiments 123 5.11 Conclusion 126 References 126 6 The TMS320C66x interrupts 127 6.1 Introduction 127 6.1.1 Chip-level interrupt controller 129 6.2 The interrupt controller 135 6.3 Laboratory experiment 140 6.3.1 Experiment 1: Using the GIPIOs to trigger some functions 140 6.3.2 Experiment 2: Using the console to trigger an interrupt 140 6.4 Conclusion 143 References 144 7 Real-time operating system: TI-RTOS 145 7.1 Introduction 146 7.2 TI-RTOS 146 7.3 Real-time scheduling 148 7.3.1 Hardware interrupts (Hwis) 148 7.3.1.1 Setting an Hwi 149 7.3.1.2 Hwi hook functions 149 7.3.2 Software interrupts (Swis), including clock, periodic or single-shot functions 155 7.3.3 Tasks 155 7.3.3.1 Task hook functions 157 7.3.4 Idle functions 158 7.3.5 Clock functions 158 7.3.6 Timer functions 158 7.3.7 Synchronisation 158 7.3.7.1 Semaphores 159 7.3.7.2 Semaphore_pend 159 7.3.7.3 Semaphore_post 159 7.3.7.4 How to configure the semaphores 159 7.3.8 Events 159 7.3.9 Summary 163 7.4 Dynamic memory management 163 7.4.1 Stack allocation 165 7.4.2 Heap allocation 165 7.4.3 Heap implementation 165 7.4.3.1 HeapMin implementation 165 7.4.3.2 HeapMem implementation 165 7.4.3.3 HeapBuf implementation 167 7.4.3.4 HeapMultiBuf implementation 171 7.5 Laboratory experiments 172 7.5.1 Lab 1: Manual setup of the clock (part 1) 172 7.5.2 Lab 2: Manual setup of the clock (part 2) 172 7.5.3 Lab 3: Using Hwis, Swis, tasks and clocks 174 7.5.4 Lab 4: Using events 187 7.5.5 Lab 5: Using the heaps 189 7.6 Conclusion 190 References 191 References (further reading) 191 8 Enhanced Direct Memory Access (EDMA3) controller 192 8.1 Introduction 192 8.2 Type of DMAs available 193 8.3 EDMA controllers architecture 194 8.3.1 The EDMA3 Channel Controller (EDMA3CC) 194 8.3.2 The EDMA3 transfer controller (EDMA3TC) 201 8.3.3 EDMA prioritisation 201 8.3.3.1 Trigger source priority 202 8.3.3.2 Channel priority 203 8.3.3.3 Dequeue priority 203 8.3.3.4 System (transfer controller) priority 203 8.4 Parameter RAM (PaRAM) 203 8.4.1 Channel options parameter (OPT) 203 8.5 Transfer synchronisation dimensions 203 8.5.1 A – Synchronisation 204 8.5.2 AB – Synchronisation 204 8.6 Simple EDMA transfer 204 8.7 Chaining EDMA transfers 208 8.8 Linked EDMAs 208 8.9 Laboratory experiments 210 8.9.1 Laboratory 1: Simple EDMA transfer 211 8.9.2 Laboratory 2: EDMA chaining transfer 211 8.9.3 Laboratory 3: EDMA link transfer 213 8.10 Conclusion 213 References 213 9 Inter-Processor Communication (IPC) 214 9.1 Introduction 215 9.2 Texas Instruments IPC 217 9.3 Notify module 219 9.3.1 Laboratory experiment 222 9.4 MessageQ 222 9.4.1 MessageQ protocol 224 9.4.2 Message priority 229 9.4.3
• Edition: 1st
• Publisher Details: Hoboken, New Jersey : John Wiley & Sons, Inc
• Publication Date: 2018
• Extent: 1 online resource
• Subjects: 621.3822; Signal processing -- Digital techniques; Texas Instruments TMS320 series microprocessors
• Languages: English
• ISBNs: 9781119003854; 9781119003830
• Related ISBNs: 9781119003823
• Notes: Note: Includes bibliographical references and index.; Note: Description based on CIP data; resource not viewed.
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