FPGA-based Implementation of Signal Processing Systems. (2017)

• Record Type: Book
• Further Information: Note: Roger Woods, John McAllister, Gaye Lightbody, Ying Yi.
• Authors: Woods, Roger; McAllister, John, 1979-; Lightbody, Gaye; Yi, Ying
• Contents: Preface xv List of Abbreviations xxi 1 Introduction to Field Programmable Gate Arrays 1 1.1 Introduction 1 1.2 Field Programmable Gate Arrays 2 1.3 Influence of Programmability 6 1.4 Challenges of FPGAs 8 Bibliography 9 2 DSP Basics 11 2.1 Introduction 11 2.2 Definition of DSP Systems 12 2.3 DSP Transformations 16 2.4 Filters 20 2.5 Adaptive Filtering 29 2.6 Final Comments 38 Bibliography 38 3 Arithmetic Basics 41 3.1 Introduction 41 3.2 Number Representations 42 3.3 Arithmetic Operations 47 3.4 Alternative Number Representations 55 3.5 Division 59 3.6 Square Root 60 3.7 Fixed-Point versus Floating-Point 64 3.8 Conclusions 66 Bibliography 67 4 Technology Review 70 4.1 Introduction 70 4.2 Implications of Technology Scaling 71 4.3 Architecture and Programmability 72 4.4 DSP Functionality Characteristics 74 4.5 Microprocessors 76 4.6 DSP Processors 82 4.7 Graphical Processing Units 86 4.8 System-on-Chip Solutions 88 4.9 Heterogeneous Computing Platforms 91 4.10 Conclusions 92 Bibliography 92 5 Current FPGA Technologies 94 5.1 Introduction 94 5.2 Toward FPGAs 95 5.3 Altera Stratix® V and 10 FPGA Family 98 5.4 Xilinx UltrascaleTM/Virtex-7 FPGA Families 103 5.5 Xilinx Zynq FPGA Family 107 5.6 Lattice iCE40isp FPGA Family 108 5.7 MicroSemi RTG4 FPGA Family 111 5.8 Design Stratregies for FPGA-based DSP Systems 112 5.9 Conclusions 114 Bibliography 114 6 Detailed FPGA Implementation Techniques 116 6.1 Introduction 116 6.2 FPGA Functionality 117 6.3 Mapping to LUT-Based FPGA Technology 123 6.4 Fixed-Coefficient DSP 125 6.5 Distributed Arithmetic 130 6.6 Reduced-Coefficient Multiplier 133 6.7 Conclusions 137 Bibliography 138 7 Synthesis Tools for FPGAs 140 7.1 Introduction 140 7.2 High-Level Synthesis 141 7.3 Xilinx Vivado 143 7.4 Control Logic Extraction Phase Example 144 7.5 Altera SDK for OpenCL 145 7.6 Other HLS Tools 147 7.7 Conclusions 150 Bibliography 150 8 Architecture Derivation for FPGA-based DSP Systems 152 8.1 Introduction 152 8.2 DSP Algorithm Characteristics 153 8.3 DSP Algorithm Representations 157 8.4 Pipelining DSP Systems 160 8.5 Parallel Operation 170 8.6 Conclusions 178 Bibliography 179 9 Complex DSP Core Design for FPGA 180 9.1 Introduction 180 9.2 Motivation for Design for Reuse 181 9.3 Intellectual Property Cores 182 9.4 Evolution of IP Cores 184 9.5 Parameterizable (Soft) IP Cores 187 9.6 IP Core Integration 195 9.7 Current FPGA-based IP Cores 197 9.8 Watermarking IP 198 9.9 Summary 198 Bibliography 199 10 AdvancedModel-Based FPGA Accelerator Design 200 10.1 Introduction 200 10.2 Dataflow Modeling of DSP Systems 201 10.3 Architectural Synthesis of Custom Circuit Accelerators from DFGs 204 10.4 Model-Based Development of Multi-Channel Dataflow Accelerators 205 10.5 Model-Based Development for Memory-Intensive Accelerators 219 10.6 Summary 223 References 223 11 Adaptive Beamformer Example 225 11.1 Introduction to Adaptive Beamforming 226 11.2 Generic Design Process 226 11.3 Algorithm to Architecture 231 11.4 Efficient Architecture Design 235 11.5 Generic QR Architecture 240 11.6 Retiming the Generic Architecture 246 11.7 Parameterizable QR Architecture 253 11.8 Generic Control 266 11.9 Beamformer Design Example 269 11.10 Summary 271 References 271 12 FPGA Solutions for Big Data Applications 273 12.1 Introduction 273 12.2 Big Data 274 12.3 Big Data Analytics 275 12.4 Acceleration 280 12.5 k-Means Clustering FPGA Implementation 283 12.6 FPGA-Based Soft Processors 286 12.7 System Hardware 290 12.8 Conclusions 293 Bibliography 293 13 Low-Power FPGA Implementation 296 13.1 Introduction 296 13.2 Sources of Power Consumption 297 13.3 FPGA Power Consumption 300 13.4 Power Consumption Reduction Techniques 302 13.5 Dynamic Voltage Scaling in FPGAs 303 13.6 Reduction in Switched Capacitance 305 13.7 Final Comments 316 Bibliography 317 14 Conclusions 319 14.1 Introduction 319 14.2 Evolution in FPGA Design Approaches 320 14.3 Big Data and the Shift toward Computing 320 14.4 Programming Flow for FPGAs 321 14.5 Support for Floating-Point Arithmetic 322 14.6 Memory Architectures 322 Bibliography 323 Index 325
• Edition: 2nd
• Publisher Details: Wiley
• Publication Date: 2017
• Extent: 1 online resource (360 pages)
• Languages: English
• ISBNs: 9781119077961
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.