Fault-Tolerance Techniques for Spacecraft Control Computers. (2017)

• Record Type: Book
• Further Information: Note: Mengfei Yang, Gengxin Hua, Yanjun Feng, Jian Gong.
• Authors: Yang, Mengfei; Hua, Gengxin; Feng, Yanjun; Gong, Jian
• Contents: Preface 8 Chapter 1 Introduction 10 1.1 Fundamental concepts and principles of fault-tolerance techniques 10 1.1.1 Fundamental concepts 10 1.1.2 Reliability principles 13 1.2 Space environment and its hazards for spacecraft control computer 19 1.2.1 Introduction to space environment 19 1.2.2 Analysis of damage caused by space environment 24 1.3 Development status and prospects of fault-tolerance techniques 30 References 33 Chapter 2 Fault Tolerance Architectures and Key Techniques 36 2.1 Fault-tolerance architecture 36 2.1.1 Module-level redundancy structures 36 2.1.2 Backup fault-tolerance structures 38 2.1.3 Triple modular redundancy (TMR) fault-tolerance structures 42 2.1.4 Other fault-tolerance structures 45 2.2 Synchronization techniques 45 2.2.1 Clock synchronization system 46 2.2.2 System synchronization method 57 2.3 Fault-tolerance design with hardware redundancy 65 2.3.1 Universal logic model and flow in redundancy design 65 2.3.2 Scheme argumentation of redundancy 66 2.3.3 Redundancy design and implementation 68 2.3.4 Validation of redundancy by analysis 73 2.3.5 Validation of redundancy by testing 77 References 78 Chapter 3 Fault Detection Techniques 80 3.1 Fault model 80 3.1.1 Fault model classified by time 80 3.1.2 Fault model classified by space 81 3.2 Fault detection techniques 83 3.2.1 Introduction 83 3.2.2 Fault detection methods for CPUs 84 3.2.3 Fault detection methods for memory 89 3.2.4 Fault detection methods for I/Os 98 References 99 Chapter 4 Bus Techniques 100 4.1 Introduction to space-borne bus 100 4.1.1 Fundamental concepts 100 4.1.2 Fundamental terminologies 100 4.2 The MIL-STD-1553B bus 101 4.2.1 Fault model of the bus system 102 4.2.2 Redundancy fault-tolerance mechanism of the bus system 106 4.3 The CAN bus 115 4.3.1 The bus protocol 116 4.3.2 Physical layer protocol and fault-tolerance 117 4.3.3 Data link layer protocol and fault tolerance 119 4.4 The SpaceWire bus 123 4.4.1 Physical layer protocol and fault-tolerance 124 4.4.2 Data link layer protocol and fault tolerance 127 4.4.3 Networking and routing 132 4.4.4 Fault-tolerance mechanism 135 4.5 Other buses 136 4.5.1 The IEEE 1394 bus 136 4.5.2 Ethernet 140 4.5.3 The I2C bus 142 References 144 Chapter 5 Software Fault-Tolerance Techniques 146 5.1 Software fault-tolerance concepts and principles 146 5.1.1 Software faults 146 5.1.2 Software fault tolerance 146 5.1.3 Software fault detection and voting 147 5.1.4 Software fault isolation 148 5.1.5 Software fault recovery 149 5.1.6 Classification of software fault-tolerance techniques 150 5.2 Single-version software fault-tolerance techniques 151 5.2.1 Checkpoint and restart 152 5.2.2 Software-implemented hardware fault tolerance 153 5.2.3 Software crash trap 157 5.3 Multiple-version software fault-tolerance techniques 157 5.3.1 Recovery blocks (RcB) 157 5.3.2 N-version programing (NVP) 159 5.3.3 Distributed recovery blocks (DRB) 159 5.3.4 N self-checking programming (NSCP) 161 5.3.5 Consensus recovery block (CRB) 162 5.3.6 Acceptance voting (AV) 163 5.3.7 Advantage and disadvantage of multiple-version software 163 5.4 Data diversity based software fault-tolerance techniques 163 5.4.1 Data re-expression algorithm (DRA) 164 5.4.2 Retry blocks (RtB) 164 5.4.3 N-copy programming (NCP) 165 5.4.4 Two-pass adjudicators (TPA) 166 References 167 Chapter 6 Fault-Tolerance Techniques for FPGA 169 6.1 Effect of space environment on FPGAs 169 6.2 Fault modes of SRAM-based FPGAs 172 6.2.1 Structure of an SRAM-based FPGA 172 6.2.2 Faults classification and fault modes analysis of SRAM-based FPGAs 175 6.3 Fault-tolerance techniques for SRAM-based FPGAs 178 6.3.1 SRAM-based FPGA mitigation techniques 179 6.3.2 SRAM-based FPGA reconfiguration techniques 186 6.4 Typical fault-tolerance design of SRAM-based FPGA 205 6.5 Fault-tolerance techniques of anti-fuse based FPGA 212 References 214 Chapter 7 Fault Injection Techniques 216 7.1 Basic concepts 216 7.1.1 Experimenter 217 7.1.2 Establishing the fault model 217 7.1.3 Conducting fault injection 217 7.1.4 Target system for fault injection 217 7.1.5 Observing the system’s behavior 217 7.1.6 Analyzing experimental findings 218 7.2 Classification of fault injection techniques 218 7.2.1 Simulated fault injection 218 7.2.2 Hardware fault injection 220 7.2.3 Software fault injection 221 7.2.4 Physical fault injection 224 7.2.5 Mixed fault injection 225 7.3 Fault injection system evaluation and application 226 7.3.1 Injection controllability 226 7.3.2 Injection observability 227 7.3.3 Injection validity 227 7.3.4 Fault injection application 227 7.4 Fault injection platform and tools 228 7.4.1 Fault injection platform in electronic design automation (EDA) environment 231 7.4.2 Computer bus-based fault injection platform 231 7.4.3 Serial accelerator based fault injection case 234 7.4.4 Future development of fault injection technology 236 References 236 Chapter 8 Intelligent Fault-Tolerance Techniques 239 8.1 Evolvable hardware fault tolerance 239 8.1.1 Fundamental concepts and principles 239 8.1.2 Evolutionary algorithm 243 8.1.3 Programmable devices 252 8.1.4 Evolvable hardware fault-tolerance implementation methods 259 8.2 Artificial immune hardware fault tolerance 273 8.2.1 Fundamental concepts and principles 273 8.2.2 Fault-tolerance methods with artificial immune system 284 8.2.3 Implementation of artificial immune fault tolerance 295 References 300 Acronyms 303 Index 307
• Edition: 1st
• Publisher Details: Wiley
• Publication Date: 2017
• Extent: 1 online resource (344 pages)
• Languages: English
• ISBNs: 9781119107415
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.