Sequential logic and Verilog HDL fundamentals. (2015)

• Record Type: Book
• Further Information: Note: Joseph Cavanagh.
• Authors: Cavanagh, Joseph
• Contents: Introduction to Verilog HDL; Built-In Primitives; User-Defined Primitives; Dataflow Modeling; Behavioral Modeling; Structural Modeling; Problems Synthesis of Synchronous Sequential Machines 1 Using Verilog HDL; Synchronous Registers; Synchronous Counters; Moore Machines; Mealy Machines; Moore–Mealy Equivalence; Output Glitches; Problems Synthesis of Synchronous Sequential Machines 2 Using Verilog HDL; Multiplexers for δ Next-State Logic; Decoders for λ Output Logic; Programmable Logic Devices; Iterative Networks; Error Detection in Synchronous Sequential Machines; Problems Synthesis of Asynchronous Sequential Machines Using Verilog HDL; Introduction; Synthesis Examples; Problems Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL; Introduction; Synthesis Examples; Problems Appendix A: Event Queue Appendix B: Verilog Project Procedure Appendix C: Answers to Select Problems
• Edition: 1st
• Publisher Details: Boca Raton : CRC Press
• Publication Date: 2015
• Extent: 1 online resource, illustrations (black and white)
• Subjects: 621.392; Verilog (Computer hardware description language); Logic design; Sequential circuits
• Languages: English
• ISBNs: 9781498738231
• Related ISBNs: 9781498738224
• Notes: Note: Description based on CIP data; item not viewed.
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.