1. Drain current model for short-channel triple gate junctionless nanowire transistors. (August 2016) Authors: Paz, B.C.; Cassé, M.; Barraud, S.; Reimbold, G.; Faynot, O.; Ávila-Herrera, F.; Cerdeira, A.; Pavanello, M.A. Journal: Microelectronics and reliability Issue: Volume 63(2016) Page Start: 1 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Drain current model for short-channel triple gate junctionless nanowire transistors. (August 2016) Authors: Paz, B.C.; Cassé, M.; Barraud, S.; Reimbold, G.; Faynot, O.; Ávila-Herrera, F.; Cerdeira, A.; Pavanello, M.A. Journal: Microelectronics and reliability Issue: Volume 63(2016) Page Start: 1 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗