1. BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. (January 2019) Authors: Qiu, Keni; Zhu, Yujie; Xu, Yuanchao; Huo, Qirun; Xue, Chun Jason Journal: Microelectronics journal Issue: Volume 83(2019) Page Start: 137 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗