Author/Creator: Sarkhel, Saheli - British Library Electronic Legal Deposit Catalogue-Journal Issues and Articles Search Results

Author/Creator Sarkhel, Saheli

1. 3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor. Issue 2 (4th March 2019)

Authors:: Saha, Priyanka; Sarkhel, Saheli; Sarkar, Subir Kumar
Journal:: IETE technical review
Issue:: Volume 36:Issue 2(2019)
Page Start:: 117
Record Type:: Journal Article
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2. A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient. (18th March 2022)

Authors:: Mukherjee, Koyel; Sau, Trisha; Upadhyay, Sneha; Mitra, Susmita; Bhowmik, Arpita; Sarkhel, Saheli; Pandit, Soumya; Pal, Rajat Kumar
Journal:: International journal of numerical modelling
Issue:: Volume 35:Number 4(2022)
Page Start:: n/a
Record Type:: Journal Article
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3. A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects. (June 2015)

Authors:: Sarkhel, Saheli; Sarkar, Subir Kumar
Journal:: Superlattices and microstructures
Issue:: Volume 82(2015)
Page Start:: 293
Record Type:: Journal Article
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4. Analytical Modeling and Performance Characterization of a Double Gate MOSFET with Dielectric Pockets Incorporating Work Function Engineered Binary Metal Alloy Gate Electrode for Subdued SCEs. Issue 5 (3rd September 2018)

Authors:: Saha, Ranita; Sarkhel, Saheli; Sarkar, Subir Kumar
Journal:: IETE technical review
Issue:: Volume 35:Issue 5(2018)
Page Start:: 506
Record Type:: Journal Article
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5. Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance. Issue 6 (1st November 2016)

Authors:: Bagga, Navjeet; Sarkhel, Saheli; Sarkar, Subir Kumar
Journal:: IETE journal of research
Issue:: Volume 62:Issue 6(2016)
Page Start:: 786
Record Type:: Journal Article
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6. Investigation of geometrical impact on a P+ buried negative capacitance SOI FET. (December 2022)

Authors:: Santra, Toushik; Dixit, Ankit; Jaisawal, Rajeewa Kumar; Rathore, Sunil; Sarkhel, Saheli; Bagga, Navjeet
Journal:: Microelectronics journal
Issue:: Volume 130(2022)
Page Start:
Record Type:: Journal Article
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