1. A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. (15th June 2010) Authors: Akram, Shoaib; Papakonstantinou, Alexandros; Kumar, Rakesh; Chen, Deming Other Names: Platzner Marco Academic Editor. Journal: International journal of reconfigurable computing Issue: Volume 2010(2010) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. (15th June 2010) Authors: Akram, Shoaib; Papakonstantinou, Alexandros; Kumar, Rakesh; Chen, Deming Other Names: Platzner Marco Academic Editor. Journal: International journal of reconfigurable computing Issue: Volume 2010(2010) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Examining the Viability of FPGA Supercomputing. (10th January 2007) Authors: Craven, Stephen; Athanas, Peter Other Names: Platzner Marco Academic Editor. Journal: EURASIP journal on embedded systems Issue: Volume 2007(2007) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model. (24th March 2015) Authors: Wang, Shupeng; Huang, Kai; Xie, Tianyi; Yan, Xiaolang Other Names: Platzner Marco Academic Editor. Journal: Journal of electrical and computer engineering Issue: Volume 2015(2015) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. (11th January 2007) Authors: Oliver, Timothy F.; Maskell, Douglas L. Other Names: Platzner Marco Academic Editor. Journal: EURASIP journal on embedded systems Issue: Volume 2007(2007) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Speeding Up FPGA Placement via Partitioning and Multithreading. (23rd December 2009) Authors: Ababei, Cristinel Other Names: Platzner Marco Academic Editor. Journal: International journal of reconfigurable computing Issue: Volume 2009(2009) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Speeding Up FPGA Placement via Partitioning and Multithreading. (23rd December 2009) Authors: Ababei, Cristinel Other Names: Platzner Marco Academic Editor. Journal: International journal of reconfigurable computing Issue: Volume 2009(2009) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗