1. Algorithmically-consistent deep learning frameworks for structural topology optimization. (November 2021) Authors: Rade, Jaydeep; Balu, Aditya; Herron, Ethan; Pathak, Jay; Ranade, Rishikesh; Sarkar, Soumik; Krishnamurthy, Adarsh Journal: Engineering applications of artificial intelligence Issue: Volume 106(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Analysis of 14nm technology node In0.53Ga0.47As nFinFET integrated with In0.52Al0.48As cap layer for high-speed circuits. Issue 10 (3rd October 2019) Authors: Pathak, Jay; Darji, Anand Journal: International journal of electronics Issue: Volume 106:Issue 10(2019) Page Start: 1514 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Assessment of interface traps in In0.53Ga0.47As FinFET with gate‐to‐source/drain underlap for sub‐14 nm technology node to impede short channel effect. Issue 4 (30th April 2019) Authors: Pathak, Jay; Darji, Anand Journal: IET circuits, devices & systems Issue: Volume 13:Issue 4(2019) Page Start: 428 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗