1. Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication. Issue 1 (9th December 2020) Authors: L., Hemanth Krishna; M., Neeharika; Janjirala, Vishvanath; Veeramachaneni, Sreehari; Mahammad S, Noor Journal: IET computers & digital techniques Issue: Volume 15:Issue 1(2021) Page Start: 12 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Efficient implementation of mixed‐precision multiply‐accumulator unit for AI algorithms. (4th March 2020) Authors: Mounica, Chandana; Krishna, Sagar; Veeramachaneni, Sreehari; Mahammad S, Noor Journal: International journal of circuit theory and applications Issue: Volume 48:Number 8(2020) Page Start: 1386 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Energy efficient signed and unsigned radix 16 booth multiplier design. (March 2021) Authors: Mounica, Y; Naresh Kumar, K; Veeramachaneni, Sreehari; Mahammad S, Noor Journal: Computers & electrical engineering Issue: Volume 90(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗